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Rendition Vérité V2200

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tools:risc_model [2026/10/12 02:33] – created - external edit 127.0.0.1tools:risc_model [2026/10/12 04:57] (current) – external edit 127.0.0.1
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 ===== Execution ===== ===== Execution =====
  
-Cycle stepping advances the model to the next SClk edge. Instruction stepping continues until an instruction retires. The F, D, X1, X2 and W display uses the core's pipeline records. Fill, Triangle, Pixel and memory timing run through the same device model.+Cycle stepping advances the model to the next SClk edge. Instruction stepping continues until an instruction retires. The F, D, X1, X2 and W display uses the core's pipeline records. A retirement is shown separately from a younger instruction still waiting in W. Fill, Triangle, Pixel and memory timing run through the same device model.
  
 The initial board preset selects the core's 4 MiB reference SGRAM model, CL3, 100 MHz and closed-row scheduling. There is no board ROM. These are emulator settings, not measured V2200 timing. The initial board preset selects the core's 4 MiB reference SGRAM model, CL3, 100 MHz and closed-row scheduling. There is no board ROM. These are emulator settings, not measured V2200 timing.
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 ===== Controls ===== ===== Controls =====
  
-''F7'' steps an instruction. ''F8'' steps a cycle. ''F9'' runs or pauses. ''Ctrl+Enter'' assembles and loads the source. Breakpoints use byte addresses. Register and memory edits require paused execution.+''F7'' steps an instruction. ''F8'' steps a cycle. ''F9'' starts Fast Run or pauses. ''Ctrl+Enter'' assembles and loads the source. Breakpoints use byte addresses. Register and memory edits require paused execution. 
 + 
 +The default example loads when the page opens and stays paused. Step first cycle records the first edge; cycle history appears once there is a recorded edge. Playback settings accept an interval in milliseconds.
  
 The run limit bounds execution. Reset clears device state, retains the loaded memory and restarts at the program's entry address. Assemble & Load clears memory before loading a new program. The trace keeps the latest 256 records. The run limit bounds execution. Reset clears device state, retains the loaded memory and restarts at the program's entry address. Assemble & Load clears memory before loading a new program. The trace keeps the latest 256 records.
 +
 +===== Cycle Data Flow =====
 +
 +Each cycle shows captured operands, forwarded values, pending results and committed register writes. Highlights use the C core's access events, including writes that store the same value. Held stages show their stall reason.
 +
 +Play cycles records every SClk edge. At short intervals, it groups up to 16 edges per request and redraws at the screen's pace. Animations and memory inspection do not set the playback delay. Fast Run samples the display while executing at full speed. The cycle history inspects recorded pipeline events; it leaves the device at its current state. The register bank is labelled Live registers, and editing is disabled while inspecting an earlier cycle.
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 +Output stays above the pipeline. Pixels refresh after steps and stops. Recent committed register results remain visible after the program halts. Display settings select the local-memory range, pixel format and zoom; PNG export keeps the original pixel dimensions.
 +
 +Instruction fields start in hex, grouped at their encoded widths. Display can instead align them to DWORDs, WORDs or bytes, or show individual bits. Changing the view leaves the program and core state unchanged.
  
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