RISC Workbench
Assemble and step the C core in the browser.
Loading the RISC core…
Core model
Model notesBreakpoints and run limit
Hex addresses, separated by commas or spaces.Output
Framebuffer
Framebuffer from local memory.
Framebuffer settings
Committed registers
No committed writes.
Pipeline dataflow
No cycles captured yet.
Last 128 captured cycles.
Step a cycle to capture pipeline activity.
R Captured read · W Committed write · P Pending result · × Discarded result. Issue numbers identify instructions across stages.
Register accesses on this edge
No captured cycle.
Select a register to open its bank. Register table values show the current core state.
Assembly
Import files
Files are read in this browser. F7: instruction · F8: cycle · F9: run/pause · Ctrl+Enter: assemble.
Source at PC
No source loaded.
Pipeline latches
| F | D | X1 | X2 | W |
|---|---|---|---|---|
| — | — | — | — | — |
Disassembly
| PC | Word | Instruction |
|---|
Instruction fields
—
| Field | Bits | Value |
|---|
Live registers
| Register | Hex value | Signed value |
|---|
R marks a captured read; W marks an actual committed write, including an unchanged value. Yellow marks a changed value. Edits are not CPU writes.
Memory
256 bytes. Edit a byte while execution is paused.
Trace
0 records · last 256 retained
| Cycle | Kind | PC | Instruction | Pipeline / stop |
|---|