Reset and Startup
Section 12 requires Reset held for 100 ms and SoftReset held for 1 ms. The PCI pin description separately says Rst# must be held for three BClk periods; the source does not reconcile these durations.
Hard reset samples XD, XA and selected MD pins, initializes memory control and starts refresh. SoftReset does not resample those straps or reset the PCI section. PClkPLL, SClkPLL and MemCtl retain programming through SoftReset.
Reset clears FIFOs, invalidates and enables DCache, and turns ICache off. It disables screen refresh requests and video outputs, selects V1000 compatibility mode, and sets RISC PC to 0xFFFFFFF0 for EPROM startup. The Debug register table also says HoldRISC is set by Reset; release/control of the boot execution depends on this hold state.
XReset asserts for hardware Reset and SoftXReset, but not for SoftReset. VGA-class strap selections enter VGA mode; other display classes enter native mode. The unconditional VGA_Mode reset wording in the Mode table conflicts with this class-dependent description.
Reset straps
| Pins | Selection |
|---|---|
| MD[30:29] | Maximum memory speed: 66.67, 83.33, 100 or 125 MHz |
| MD[33], MD[35] | Memory type and latency |
| MD[40:38], MD[43:41] | Chip-select memory-size fields |
| MD[44], MD[62:61] | Banks per chip and address swizzle |
| XD[3:0] | Maximum RISC clock |
| XD[4] | TestMode# |
| XD[5] | PLL versus direct clocks |
| XD[7:6] | VGA, Multimedia or Other Display class |
| XA[3:0] | DAC / PLL test selections |
The source uses 2.2 kΩ pull-up/pull-down resistors to select one/zero. If XA[3:1] is zero and XD[5] is one, the chip enters TestClkMode. Full strap diagrams are in Reset pin formats.
A zero drawn in a register diagram is a schematic value unless explicitly labelled as a reset value. Straps, unaffected registers and unspecified fields prevent assuming a single all-zero startup state.
Default PLL settings · Conflicting reset descriptions
Sources: Technical Spec, p.42, Technical Spec, p.44, Technical Spec, p.48, Technical Spec, p.57, Technical Spec, p.61, Technical Spec, p.62