Interface Timing

These are external signal timings. They are separate from RISC result delays and drawing-engine launch times.

Memory Write

Measured at the memory chips. All values are minimum nanoseconds.

Symbol	Signal / condition	V2200	V2200-60
ts	Data setup before write	4.0	3.0
th	Data hold after write	2.5	1.5
tdsz	Data setup from tri-state	3.5	2.5
tcs	Control/address setup	4.0	3.0
tch	Control/address hold	2.6	1.6

Measured at V2200. All values are minimum nanoseconds.

Symbol	Condition	V2200	V2200-60
trds	Data setup	2.0	1.75
trdh	Data hold	2.0	1.75

The figure caption on page 64 says memory write, but its table and signals describe memory read.

Symbol	Signals	Minimum
tvs	Setup for VIn[7:0], Active, VBlank, HSync and VSync before VInClk	5.0 ns
tvh	Hold for those signals after VInClk	0.0 ns

BClk in these expressions is the PCI clock period in nanoseconds.

Symbol	Condition	Time (ns)
txwp	Minimum write pulse	4 × BClk − 3
txrp	Minimum read pulse	4 × BClk − 3
txads	Address setup before access; data setup before write	2 × BClk − 3
txadh	Address hold after access; data hold after write	2 × BClk − 3
txrs	Read data setup to XRd or XWait	10
txrh	Read data hold from XRd	0
txp	Minimum precharge between accesses	3 × BClk − 3