Interrupts and Status
Host interrupt status is in Intr, with corresponding enables in IntrEn. Status can be asserted while its interrupt is disabled. Most latched status bits clear by writing one; writes of zero are ignored where specified.
| Event | Host Intr bit | RISC riscintr bit |
|---|---|---|
| Vertical retrace | 0 | 0 |
| Input FIFO low-water threshold | 1 | — |
| RISC firmware signal | 2 | — |
| RISC halt | 3 | — |
| FIFO access error | 4 | — |
| DMA error / DMA complete | 5 / 6 | — |
| External XIntr | 7 | 1 |
| Video input even / odd field | 8 / 9 | 2 / 3 |
| Chip idle | 10 | — |
| Memory write match 0 / 1 | 11 / 12 | 4 / 5 |
The register named riscintr is polled by microcode. It does not asynchronously redirect RISC execution. Its bit 31 is asserted when any enabled RISC interrupt is pending; dispatch code branches to the appropriate handler. Enable bits occupy 16..21.
Writing Flag.SignalSys sets and holds a host interrupt. The Flag prose says to clear a RISCIntr bit in Comm, but Comm contains only status fields; the explicit host table assigns RISCIntr to Intr[2]. This mismatch is SIGNAL_CLEAR_REGISTER. Odd-field interrupt descriptions also incorrectly repeat “even field”; their precise event wording remains unresolved.
Communication and idle
Comm exchanges four-bit SysStatus and RISCStatus values. The host writes SysStatus; RISC code reads it in Flag[11:8]. The RISC writes Flag.Status; the host reads it as Comm[7:4]. Flag writes have a three-instruction hazard and the source gives a three-delay host visibility interval.
Status.Idle is true when the RISC is halted, held, or stalled on a FIFO, and Pixel/Triangle and Fill are idle. Flag.PixelBusy includes all three drawing engines.
Hold and context switching · Capture interrupts
Sources: Technical Spec, p.25, Technical Spec, p.27, Technical Spec, p.41, Technical Spec, p.42, Technical Spec, p.43