Source Issues
The specification contains conflicting addresses, field descriptions and timing statements. The register conversion uses the detailed field table where one exists, and keeps the conflicting wording visible. Undefined fields are not filled in from an assumed chip model.
SIGNAL_CLEAR_REGISTER
Flag.SignalSys description puts RISCIntr in Comm, while Comm only contains status nibbles and Intr[2] is explicitly RISCIntr.
Intr[2] is the host RISC interrupt bit in the register diagram. The Comm reference in the Flag description conflicts with Table 5.5.
References: %37 / flag · Intr / IO +0x44 · Comm / IO +0x42
SEG_RANGE
Seg2 is written as 11:8, but pointers are said to be 3 bits, the formula masks with 7, and bit 11 always reads 1.
The diagram assigns the Seg2 pointer to bits 10:8 and constant one to bit 11. This follows the index formula; the prose range disagrees.
References: %35 / seg
ODD_FIELD
Descriptions of VInOddIntr and VideoInOddIntr both say end of even field.
The odd-field names remain in the diagrams. The field-end description is unresolved.
References: %47 / riscintr · Intr / IO +0x44
FILL_CSOURCE
Page 21 restricts cbrush8 to 8/16 bpp and cbrush16 is implied broader; Tables 2.11a/c and startup table explicitly include cbrush8 32 bpp and restrict cbrush16 to 8/16 bpp.
The alternate views follow the explicit parameter tables: cbrush8 supports 8/16/32 bpp, cbrush16 supports 8/16 bpp, and cbrush32 supports 8 bpp.
References: %136 / a8 / R2 · %137 / a9 / F · %138 / a10 / G2 · %139 / a11 / B2 · %140 / a12 / U · %141 / a13 / V · %142 / a14 / dXLong/dy · %143 / a15 / n/a
DRAW_PAIR3_TEXT
Embedded extracted text gives XShadow=X for pair1=3, but the rendered PDF table shows N/A.
The DrawCtl diagram uses N/A for this XShadow entry, as shown in the rendered PDF.
References: %40 / npswfifo / drawctl · DrawCtl / StateIndex 131
FIFO_COUNTS
Input/output FIFO depths are 32/8, while count fields are given as 5/3 bits and cannot encode 32/8.
The diagrams retain the stated field widths. Encoding of an empty FIFO's full free count, or a completely full FIFO's valid count, is unspecified.
References: FIFOInFree / IO +0x40 · FIFOOutValid / IO +0x41
XBUS_BLANK
XBusWaitBlank wording says “If 0 set” on p43; p43/55 give front porch+sync, p66 gives back porch+sync.
Bit polarity and the permitted horizontal porch remain unresolved.
References: XBusCtl / IO +0x4B
Technical Spec, p.43, Technical Spec, p.55, Technical Spec, p.66
MODE_RESET
Mode table says VGA_Mode is set by Reset, while Sections 11/12 say native after reset for non-VGA device classes.
The reset description is conditional on the selected PCI device class. A full-byte Mode reset value is not specified.
References: Mode / IO +0x72
Technical Spec, p.44, Technical Spec, p.57, Technical Spec, p.61
MEM_CS0
MemCtl[4:2] is “User defined” on p44, but matching reset pins MD[40:38] initialize MemSizeCS0 on p61.
The diagram retains both names and the MD[40:38] strap source. The function of MemCtl[4:2] remains unresolved.
References: MemCtl / IO +0xA0
CRTC_TEST_WIDTH
Native map mentions writable bits 4:0 only, but detailed table additionally defines writable 15:5 and read-only 16/18.
The diagram includes the fields defined in detailed Table 5.14b.
References: CRTCTest / IO +0x80
VOUT_CONTROL
Section 9 locates VOutEn in CRTCCtl, but CRTCCtl has no VOutEn bit and Table 5.15a explicitly places it at PClkPLL[19].
The diagram assigns VOutEn to PClkPLL[19], following Table 5.15a.
References: CRTCCtl / IO +0x84 · PClkPLL / IO +0xC0
Technical Spec, p.46, Technical Spec, p.48, Technical Spec, p.55
RISC_MAP_OVERVIEW
Table 5 overview gives coarse CRTC/PLL/VIn address ranges inconsistent with detailed per-register addresses (e.g. SClkPLL 0xffe00620, VInOddBase 0xffe006a0).
The register pages use addresses from the detailed per-register tables.
References: SClkPLL / IO +0x68 · VInOddBase / IO +0xD4
Technical Spec, p.38, Technical Spec, p.40, Technical Spec, p.48, Technical Spec, p.53
WRITE_INTR_GRANULARITY
Interrupt descriptions use byte-address matching, but Table 8a defines address[23:3] and a double-word match.
The diagram retains address bits 23:3. The exact write-match granularity remains unresolved.
References: WriteIntr0Adr / IO +0xD8 · WriteIntr1Adr / IO +0xDC
Technical Spec, p.27, Technical Spec, p.41, Technical Spec, p.42, Technical Spec, p.53
PALETTE_BA
IO +0xBA is Command4/signature analysis in Table 7a and palette Status with completely different fields in Table 7b.
The diagram shows the detailed Palette Status fields. The Command4/signature-analysis description remains unresolved.
References: Palette Status / IO +0xBA
VGA_ATTR_WORDING
Attribute index text says Graphics register; Attribute mode bit0 named Graphics is described as color/mono, and bit7 polarity is retained from this source without importing standard VGA corrections.
The diagrams retain the Attribute table names and literal bit descriptions. The conflicting wording is unresolved.
References: Attribute index · Attribute[10] / Attribute mode
DRAW_TIMING
Page14 says draw takes 3 cycles but also gives launch=2+2*ParamPairs and draw3=8.
The opcode details list both source timings. The document does not establish a single consistent launch-time rule.
Additional Wording Notes
| Pages | Wording | Reading used on the overview pages |
|---|---|---|
| 29, 33 | AlphaThres summary says destination alpha; DstMode.TranspReject says texture-unit output alpha. | Destination processing follows the detailed DstMode field. |
| 30, 36 | ChromaKey prose calls indexed 1555 “SrcFunc = 0xA”; SrcFunc is defined only from 0 to 3. | The SrcMode table places indexed 1555 at SrcFmt = 0xA. |
| 61, 62 | Reset is 100 ms in Section 12; Rst# pin text says three BClk periods. | No combined reset-duration rule is assumed. |
| 62 | The PCI introduction says 66 MHz, BClk prose says up to 33 MHz, and timing gives a 15 ns minimum period. | The contradictory prose does not establish board clock support. |
| 42, 61 | Debug.HoldRISC is set by reset; the reset sequence says the RISC starts executing EPROM at 0xFFFFFFF0. | The hold state and entry PC are documented; a release sequence is not supplied here. |
Technical Spec, p.29, Technical Spec, p.30, Technical Spec, p.33, Technical Spec, p.36, Technical Spec, p.42, Technical Spec, p.61, Technical Spec, p.62
Derived Views
Tex4Pal channel diagrams are optional conventional 565/4444/1555 interpretations. The PDF explicitly defines only the two sixteen-bit color halves and their selected format. It does not show their internal channel fields or the SrcBGR swap stage. The default view remains the documented halves.
Seg2 pointer bits 10:8 are selected from the supplied index formula and constant bit 11. The conflicting prose range remains listed above.