PCI / Host Interface
The V2200 exposes local memory, BIOS ROM, native I/O ports and memory-mapped registers. PCI configuration identifies Vendor 0x1163, Device 0x2000. Reset straps select VGA Display, Other Display or Multimedia class.
| Aperture | Allocation |
|---|---|
| Local memory | 16 MB, independent of installed memory capacity |
| BIOS ROM | 128 KB |
| Native I/O | 256 bytes |
| Native MMIO | 256 KB |
Native register addresses are byte offsets from their allocated base. Control-register byte offsets assume a little-endian host. I/O byte order does not change with MemEndian. MMIO FIFO regions repeat each swap alias over a 32 KB range, allowing string transfers.
| I/O offset | FIFO swap | MMIO range |
|---|---|---|
+0x00 | None | 0x00000..0x07FFC |
+0x04 | Reverse bytes: B3↔B0, B2↔B1 | 0x08000..0x0FFFC |
+0x08 | B3↔B2, B1↔B0 | 0x10000..0x17FFC |
+0x0C | B3↔B1, B2↔B0 | 0x18000..0x1FFFC |
FIFO writes send 32-bit words to the input command FIFO. Reads obtain output FIFO words. Host writes while input is full, or reads while output is empty, set FIFOErrorIntr; these accesses require software flow control.
Memory synchronization
PCI accesses to local memory can occur at any time. To maintain coherency with Pixel Engine data, wait for Pixel idle unless the code establishes that the accessed addresses do not overlap. The source also recommends RISC and Pixel idle for best PCI memory performance. Direct frame-buffer accesses bypass rendering engines.
Native and PCI register maps · Byte swapping · DMA command lists · Interrupts
Sources: Technical Spec, p.19, Technical Spec, p.38, Technical Spec, p.39, Technical Spec, p.40