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Rendition Vérité V2200

RISC Opcodes

OP occupies bits 31:24 of the 32-bit instruction. Select an opcode for operands, operation, hazards and its instruction format.

Opcode byte — high nibble rows, low nibble columns
OP0123456789ABCDEF
0000add immediate01sub immediate02andn immediate03subf immediate04and immediate05or immediate06nor immediate07xor immediate08mul immediate09mulsr8 immediate0Amulsr16 immediate0Bmulsr24 immediate0Cmulsr32 immediate0Dmulsr31 immediate0Eclip immediate0Ff2i immediate
1010add11sub12andn13subf14and15or16nor17xor18mul19mulsr81Amulsr161Bmulsr241Cmulsr321Dmulsr311Eclip1Ff2i
2020addv21subv22andnv23subfv24andv25orv26norv27xorv28mulv29mulsr8v2Amulsr16v2Bmulsr24v2Cmulsr32v2Dmulsr31v2Eclipv2F—
3030addvs31subvs32andnvs33subfvs34andvs35orvs36norvs37xorvs38mulvs39mulsr8vs3Amulsr16vs3Bmulsr24vs3Cmulsr32vs3Dmulsr31vs3Eclipvs3F—
4040addif41subif42seedsr immediate43subfif44rotr immediate45sl immediate46asr immediate47sr immediate48slt immediate49sltu immediate4Aseq immediate4Baddsl84Cmin immediate4Dmax immediate4Esprii4Fspri
5050—51—52abs53seedsr54rotr55sl56asr57sr58slt59sltu5Aseq5B—5Cmin5Dmax5Eat5Fspr
6060bez61bnez62bgez63blz64bgz65blez66—67—68rjmp69—6Arjmpl6Bgetpc6Cjmp6Dhalt6Ejmpl6Fjmprl
7070lb71lh72lw73pre74lv75lvra76li77lui78sb79sh7Asw7B—7Csv7Dsy7Escr7Fscb
8080—81—82—83—84—85—86—87—88—89—8A—8B—8C—8D—8E—8F—
9090—91—92—93—94—95—96—97—98—99—9A—9B—9C—9D—9E—9F—
A0A0—A1—A2—A3—A4—A5—A6—A7—A8—A9—AA—AB—AC—AD—AE—AF—
B0B0—B1—B2—B3—B4—B5—B6—B7—B8—B9—BA—BB—BC—BD—BE—BF—
C0C0getxyC1getyxC2getraC3getgbC4sortC5—C6—C7—C8—C9—CA—CB—CC—CD—CE—CF—
D0D0step x/yD1step qD2step r/vD3step i/uD4step fD5step g/bD6step z/aD7step cntD8stepv xyD9stepv quDAstepv rvDBstepv ivDCstepv zvDDstepv gbDEstepv zaDFstepv cnt
E0E0drawpE1rdrawpE2—E3—E4drawpxyE5rdrawpxyE6—E7mbltfoE8fillE9mbrushEAmbltEBmbltfECcbrush8EDcbrush16EEcbrush32EFcbltf
F0F0draw1F1rdraw1F2draw2F3rdraw2F4—F5—F6—F7—F8draw3F9rdraw3FAdraw4FBrdraw4FCdraw5FDrdraw5FEtriFF—

An empty cell has no definition in this specification.

Opcode Details

OPMnemonicOperandsWhat it doesTiming
0x00add immediateD,S2,uimm8D=S2+S1result delay 0
0x01sub immediateD,S2,uimm8D=S2-S1result delay 0
0x02andn immediateD,S2,uimm8D=S2 AND NOT S1result delay 0
0x03subf immediateD,S2,uimm8D=S1-S2result delay 0
0x04and immediateD,S2,uimm8D=S2 AND S1result delay 0
0x05or immediateD,S2,uimm8D=S2 OR S1result delay 0
0x06nor immediateD,S2,uimm8D=S2 NOR S1result delay 0
0x07xor immediateD,S2,uimm8D=S2 XOR S1result delay 0
0x08mul immediateD,S2,uimm8D=low32(S2*S1)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x09mulsr8 immediateD,S2,uimm8D=low32((S2*S1)>>8)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x0Amulsr16 immediateD,S2,uimm8D=low32((S2*S1)>>16)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x0Bmulsr24 immediateD,S2,uimm8D=low32((S2*S1)>>24)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x0Cmulsr32 immediateD,S2,uimm8D=low32((S2*S1)>>32)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x0Dmulsr31 immediateD,S2,uimm8D=low32((S2*S1)>>31)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x0Eclip immediateS2,uimm8Clip=(Clip<<1)&0xfc | ((signed(S2-S1)>0)?4:0)Clip read hazard 1
0x0Ff2i immediateD,S2,uimm8Convert IEEE754 S2 * 2^S1, floor toward -infinity, saturate; 0<=S1<=30result delay 0
0x10addD,S2,S1D=S2+S1result delay 0
0x11subD,S2,S1D=S2-S1result delay 0
0x12andnD,S2,S1D=S2 AND NOT S1result delay 0
0x13subfD,S2,S1D=S1-S2result delay 0
0x14andD,S2,S1D=S2 AND S1result delay 0
0x15orD,S2,S1D=S2 OR S1result delay 0
0x16norD,S2,S1D=S2 NOR S1result delay 0
0x17xorD,S2,S1D=S2 XOR S1result delay 0
0x18mulD,S2,S1D=low32(S2*S1)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x19mulsr8D,S2,S1D=low32((S2*S1)>>8)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x1Amulsr16D,S2,S1D=low32((S2*S1)>>16)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x1Bmulsr24D,S2,S1D=low32((S2*S1)>>24)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x1Cmulsr32D,S2,S1D=low32((S2*S1)>>32)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x1Dmulsr31D,S2,S1D=low32((S2*S1)>>31)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x1EclipS2,S1Clip=(Clip<<1)&0xfc | ((signed(S2-S1)>0)?4:0)Clip read hazard 1
0x1Ff2iD,S2,S1Convert IEEE754 S2 * 2^S1, floor toward -infinity, saturate; 0<=S1<=30result delay 0
0x20addvD,S2,S1D=S2+S1result delay 0
0x21subvD,S2,S1D=S2-S1result delay 0
0x22andnvD,S2,S1D=S2 AND NOT S1result delay 0
0x23subfvD,S2,S1D=S1-S2result delay 0
0x24andvD,S2,S1D=S2 AND S1result delay 0
0x25orvD,S2,S1D=S2 OR S1result delay 0
0x26norvD,S2,S1D=S2 NOR S1result delay 0
0x27xorvD,S2,S1D=S2 XOR S1result delay 0
0x28mulvD,S2,S1D=low32(S2*S1)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x29mulsr8vD,S2,S1D=low32((S2*S1)>>8)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x2Amulsr16vD,S2,S1D=low32((S2*S1)>>16)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x2Bmulsr24vD,S2,S1D=low32((S2*S1)>>24)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x2Cmulsr32vD,S2,S1D=low32((S2*S1)>>32)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x2Dmulsr31vD,S2,S1D=low32((S2*S1)>>31)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x2EclipvS2,S1Clip=(Clip<<1)&0xfc | ((signed(S2-S1)>0)?4:0)Clip read hazard 1
0x30addvsD,S2,S1D=S2+S1result delay 0
0x31subvsD,S2,S1D=S2-S1result delay 0
0x32andnvsD,S2,S1D=S2 AND NOT S1result delay 0
0x33subfvsD,S2,S1D=S1-S2result delay 0
0x34andvsD,S2,S1D=S2 AND S1result delay 0
0x35orvsD,S2,S1D=S2 OR S1result delay 0
0x36norvsD,S2,S1D=S2 NOR S1result delay 0
0x37xorvsD,S2,S1D=S2 XOR S1result delay 0
0x38mulvsD,S2,S1D=low32(S2*S1)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x39mulsr8vsD,S2,S1D=low32((S2*S1)>>8)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x3Amulsr16vsD,S2,S1D=low32((S2*S1)>>16)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x3Bmulsr24vsD,S2,S1D=low32((S2*S1)>>24)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x3Cmulsr32vsD,S2,S1D=low32((S2*S1)>>32)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x3Dmulsr31vsD,S2,S1D=low32((S2*S1)>>31)1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x3EclipvsS2,S1Clip=(Clip<<1)&0xfc | ((signed(S2-S1)>0)?4:0)Clip read hazard 1
0x40addifD,S2,uimm8D=S2+(uimm8<<16)0
0x41subifD,S2,uimm8D=S2-(uimm8<<16)0
0x42seedsr immediateD,S2,uimm8Same seedsr operation with immediate S1.2
0x43subfifD,S2,uimm8D=(uimm8<<16)-S20
0x44rotr immediateD,S2,uimm8Rotate S2 right by S1.0; branch-decision result interlock 1
0x45sl immediateD,S2,uimm8Logical shift left by S1&31.0; branch interlock 1
0x46asr immediateD,S2,uimm8Arithmetic shift right by S1&31.0; branch interlock 1
0x47sr immediateD,S2,uimm8Logical shift right by S1&31.0; branch interlock 1
0x48slt immediateD,S2,uimm8D=(signed(S2)<signed(S1)) ? 1 : 00
0x49sltu immediateD,S2,uimm8Unsigned comparison.0
0x4Aseq immediateD,S2,uimm8D=(S2==S1) ? 1 : 00
0x4Baddsl8D,S2,uimm8D=S2+(uimm8<<8)0
0x4Cmin immediateD,S2,uimm8D=min(S2,S1)0
0x4Dmax immediateD,S2,uimm8D=max(S2,S1)0
0x4Espriireg,immed16PixRegSpecifiedBy(reg)=immed16Triangle shadow destination -> spr hazard 2
0x4Fsprireg,S2PixRegSpecifiedBy(reg)=S2Triangle shadow destination -> spr hazard 2
0x52absD,S1D=abs(S1)0
0x53seedsrD,S2,S1D=seed(S2)>>(scale(S2)-S1); shift range 0..30. Updates seed, scale, index. See fill hazard.2
0x54rotrD,S2,S1Rotate S2 right by S1.0; branch-decision result interlock 1
0x55slD,S2,S1Logical shift left by S1&31.0; branch interlock 1
0x56asrD,S2,S1Arithmetic shift right by S1&31.0; branch interlock 1
0x57srD,S2,S1Logical shift right by S1&31.0; branch interlock 1
0x58sltD,S2,S1D=(signed(S2)<signed(S1)) ? 1 : 00
0x59sltuD,S2,S1Unsigned comparison.0
0x5AseqD,S2,S1D=(S2==S1) ? 1 : 00
0x5CminD,S2,S1D=min(S2,S1)0
0x5DmaxD,S2,S1D=max(S2,S1)0
0x5EatD,S2,S1D=(S2+S1)&0xffff00000
0x5Fspr(S1),S2PixRegSpecifiedBy(S1)=S2Triangle shadow destination -> spr hazard 2
0x60bezS1,offset16If S1==0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported.one non-annulling delay slot
0x61bnezS1,offset16If S1!=0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported.one non-annulling delay slot
0x62bgezS1,offset16If S1>=0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported.one non-annulling delay slot
0x63blzS1,offset16If S1<0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported.one non-annulling delay slot
0x64bgzS1,offset16If S1>0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported.one non-annulling delay slot
0x65blezS1,offset16If S1<=0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported.one non-annulling delay slot
0x68rjmpaddrRelative jump to delay-slot PC+addr*4one non-annulling delay slot
0x6ArjmpladdrRelative jump and link in raone non-annulling delay slot
0x6BgetpcDJump never, link in Dno delay slot
0x6Cjmpaddr24Absolute jump to addr24<<2; MSB selects ROMone non-annulling delay slot
0x6DhaltcauseHalt RISC; optional cause; last executed instructionno delay slot
0x6Ejmpladdr24Absolute jump and link in raone non-annulling delay slot
0x6FjmprlD,(S1)Jump to S1 and link in Done non-annulling delay slot
0x70lbD,offset8(S1)Unsigned byte load; address=S1+offset8load interlock 1; pre/li/lui 0
0x71lhD,offset8(S1)Unsigned halfword load; address=S1+offset8*2; halfword alignedload interlock 1; pre/li/lui 0
0x72lwD,offset8(S1)Word load; address=S1+offset8*4; word alignedload interlock 1; pre/li/lui 0
0x73preoffset8(S1)Prefetch S1+offset8*8load interlock 1; pre/li/lui 0
0x74lvD,offset8(S1)Load even/odd pair at S1+offset8*8; double-word alignedload interlock 1; pre/li/lui 0
0x75lvraD,offset8(S1)Vector load plus prefetch next double wordload interlock 1; pre/li/lui 0
0x76liD,immed16D=unsigned immed16load interlock 1; pre/li/lui 0
0x77luiD,immed16D=immed16<<16load interlock 1; pre/li/lui 0
0x78sboffset8(S1),S2Byte store at S1+offset8
0x79shoffset8(S1),S2Halfword store at S1+offset8*2
0x7Aswoffset8(S1),S2Word store at S1+offset8*4
0x7Csvoffset8(S1),S2Store even/odd pair at S1+offset8*8; double-word aligned
0x7Dsyoffset8(S1),S2Store S2 bytes at offsets 0,2,4,6 from S1+offset8*8; other bytes unchanged
0x7Escroffset8(S1),S2Store S2 bytes at offsets 1,5,9,13; quad-word alignedscr takes two DCache cycles
0x7Fscboffset8(S1),S2Store S2 bytes at offsets 3,7,11,15 from S1+offset8*8; quad-word aligned; other bytes unchanged.two DCache cycles
0xC0getxyD,S1Deven=S1&0xffff0000; Dodd=S1<<160
0xC1getyxD,S1Deven=S1<<16; Dodd=S1&0xffff00000
0xC2getraD,S1D0=S1&0xff0000; D1=(S1>>8)&0xff00000
0xC3getgbD,S1D0=(S1<<8)&0xff0000; D1=(S1<<16)&0xff00000
0xC4sortS3,S2,S1Sorts register indices into Seg0/1/2 by values. Ties: S1 smallest then S2. Shifts four identical flags into Clip based on ceil(max)-1 < ceil(min).2 cycles; Seg hazard 3, Clip hazard 2
0xD0step x/yD,S2,S1Even S2 updates XShadow and XDir from sign(S1); odd S2 updates Y. 16I.16F. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD1step qD,S2,S1Seed operation; Q 0I.24F. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD2step r/vD,S2,S1Even S2 updates R; odd updates V and VDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD3step i/uD,S2,S1Even updates R=G=B=intensity; odd updates U and UDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD4step fD,S2,S1Odd S2 updates fog factor. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD5step g/bD,S2,S1Even updates G; odd updates B. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD6step z/aD,S2,S1Even updates Z 21I.11F; odd Alpha 16I.16F. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD7step cntD,S2,S1Even S2 updates Count from bits31:16. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD8stepv xyD,S2,S1Vector XShadow/XDir and Y. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xD9stepv quD,S2,S1Vector Q seed and U/UDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xDAstepv rvD,S2,S1Vector R and V/VDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xDBstepv ivD,S2,S1Vector RGB intensity and V/VDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xDCstepv zvD,S2,S1Vector Z 21I.11F and V 16I.16F. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xDDstepv gbD,S2,S1Vector G and B. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xDEstepv zaD,S2,S1Vector Z and Alpha. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xDFstepv cntD,S2,S1Vector Count; extra odd add. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F.Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2
0xE0drawpD,S2,S1Single parallel draw; update XShadow and U. Unsigned Count. Parallel pixels/cycle = 4/sizeof(pixel). SwapUV must be zero, masks all ones, clamps disabled.Count or XShadow setup hazard 1; DrawCtl hazard 3
0xE1rdrawpD,S2,S1Repeated parallel draw; update XShadow and U. Unsigned Count. Parallel pixels/cycle = 4/sizeof(pixel). SwapUV must be zero, masks all ones, clamps disabled.Count or XShadow setup hazard 1; DrawCtl hazard 3
0xE4drawpxyD,S2,S1Single resetting parallel draw. Unsigned Count. Parallel pixels/cycle = 4/sizeof(pixel). SwapUV must be zero, masks all ones, clamps disabled.Count or XShadow setup hazard 1; DrawCtl hazard 3
0xE5rdrawpxyD,S2,S1Repeated resetting parallel draw. Unsigned Count. Parallel pixels/cycle = 4/sizeof(pixel). SwapUV must be zero, masks all ones, clamps disabled.Count or XShadow setup hazard 1; DrawCtl hazard 3
0xE7mbltfoD,S2,S1Opaque monochrome FIFO BitBlt. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xE8fillD,S2,S1Solid color fill. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xE9mbrushD,S2,S1Transparent monochrome brush. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xEAmbltD,S2,S1Transparent monochrome BitBlt using a8-a15. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xEBmbltfD,S2,S1Transparent monochrome FIFO BitBlt. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xECcbrush8D,S2,S1Eight-pixel color brush. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xEDcbrush16D,S2,S1Sixteen-pixel color brush. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xEEcbrush32D,S2,S1Thirty-two-pixel color brush. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xEFcbltfD,S2,S1Color FIFO BitBlt; format bit7 enables chroma key. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255.1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3
0xF0draw1D,S2,S11 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xF1rdraw1D,S2,S11 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xF2draw2D,S2,S12 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xF3rdraw2D,S2,S12 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xF8draw3D,S2,S13 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xF9rdraw3D,S2,S13 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xFAdraw4D,S2,S14 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xFBrdraw4D,S2,S14 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xFCdraw5D,S2,S15 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xFDrdraw5D,S2,S15 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q.source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING
0xFEtriD,S2,S1Launch triangle; prelaunch vector add can update xy,zq,uv,ra,gb,r2f,g2b2. DrawCtl[3:0]=0xB; shadowed registers and DrawCtl writes stall while triangle busy.1-cycle launch; total=4+scanlines+pixels excluding memory stalls; tri -> fill hazard 3
risc/opcodes.txt · Last modified: by 127.0.0.1