Pixel Engine
The Pixel Engine receives drawing parameters from RISC draw/step instructions or the Triangle Engine. It applies texture sampling, source color operations, visibility tests, blending, fog, dithering and plane masks before writing local memory.
State writes
spr, spri and sprii write a complete register or a register field. The selector is the spr index; the value comes from S2 or the immediate operand. A field write retains its original bit position within the operand. It is not shifted down to bit zero.
Pixel Engine mode registers are pipelined. The specification says they can be written without waiting for Pixel idle. Coherent PCI memory access and final readback require separate synchronization; see Host interface and Context switching.
| State group | Registers / reference |
|---|---|
| Texture | SrcBase, SrcMode, SrcMask, texture sampling |
| Addressing | DstBase, ZBase, Stride |
| Output | DstMode, DstFmt, PMask, destination processing |
| Visibility | ScissorX, ScissorY, AlphaThres, Pick |
| Pattern | Pattern, PatMode and PatOffset |
| Colors | FGColor, BGColor, FogColor, SpecColor |
| Conversion | YUV-to-RGB conversion |
Scissors use half-open ranges: L ≤ X < R and T ≤ Y < B, also requiring 0 ≤ coordinate < 2048. DstBase must be word aligned; ZBase must be half-word aligned. SrcBase is byte aligned, except YUYV sources require word alignment.
spr Sync is unconditional when bit 16 is clear: it waits for prior drawing commands to complete. When bit 16 is set it waits only if destination or Z data is being read.
Sources: Technical Spec, p.28, Technical Spec, p.29