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Rendition Vérité V2200

Instruction Hazards

Interlocked delay stalls the pipeline when a result is required too early. Non-interlocked hazard requires instruction scheduling in microcode. Special registers are never forwarded.

Producer → consumer Required interval / effect Source
Memory load → dependent instruction Interlocked delay 1 p.9
Scalar multiply → dependent instruction Delay 1 p.8
Shift result → branch decision Interlocked delay 1 p.8
Write Flag, Timer or Seg → read/use Hazard 3 pp.6–7, 25–26
clip / clipv → Clip read Hazard 1 p.7
sort → Seg / Clip read Seg hazard 3; Clip hazard 2 p.9
Seed operation → Scale / seed index / Seed Scale and index hazard 1; Seed hazard 2 p.7
Write Triangle Engine shadow destination → spr / spri / sprii Hazard 2 p.9
step Cnt / stepv Cnt → draw Hazard 1 p.12
Set XShadow → parallel draw Hazard 1; no such hazard for parameterized draw pp.13–14
Write DrawCtl → compatibility draw Hazard 3 pp.13–14
Enable V2000 mode → set shadow registers No hazard specified p.16
tri → Fill Engine instruction Hazard 3 p.16
Fill instruction → seed-generating instruction Three-instruction hazard; seed descriptions say to issue more than three instructions later pp.8, 12, 22
Fill instruction → draw / rdraw At least one separating instruction p.22

Fill parameter writes have their own hazards: format and offset 3, write mask 1, color/key 2, brush or source data 3. See Fill parameter registers.

The PDF sometimes describes intervals as cycles and sometimes as instructions. The table preserves the supplied values; instruction launch time and engine completion time are listed separately in opcode details.

Engine stalls

Writing DrawCtl, a0..a31 or q0..q15 while the Triangle Engine is busy stalls the RISC until it becomes idle. A triangle or parameterized draw reached while Fill is busy also waits. Fill waits for Pixel and Triangle idle before launch.

During FIFO-sourced fills, InputFIFO reads and shifter instructions stall until the fill completes. mbltfo also stalls writes to a8. Most fill parameters can otherwise be overwritten after launch because they are shadowed or consumed at startup.

Sources: Technical Spec, p.6, Technical Spec, p.7, Technical Spec, p.8, Technical Spec, p.9, Technical Spec, p.12, Technical Spec, p.13, Technical Spec, p.14, Technical Spec, p.16, Technical Spec, p.22, Technical Spec, p.24

risc/hazards.txt · Last modified: (external edit)