V2200 Architecture
The V2200 integrates a 32-bit RISC processor, Triangle Engine, Pixel Engine, Fill Engine, PCI bus-master interface, VGA core, CRTC and RAMDAC. Local memory is shared by rendering, display refresh, the RISC and PCI accesses. The memory interface supports 2 to 16 MB of SGRAM or SDRAM on a 64-bit data bus.
| Block | Function | Programming reference |
|---|---|---|
| RISC | Executes microcode, reads command FIFO data and launches drawing operations. | RISC programming |
| Triangle Engine | Walks edges and spans; iterates vertex parameters and performs perspective correction. | Triangle drawing |
| Pixel Engine | Samples textures; applies visibility tests, blending, fog, dithering and plane masks. | Pixel operations |
| Fill Engine | Writes scan lines of solid, monochrome or color data. | Memory fills |
| PCI interface | Maps local memory and control registers; transfers command data by DMA. | Host interface |
| CRTC / RAMDAC | Reads the display surface and produces analog or digital video. | Display control |
| VGA | Provides text and graphics compatibility through mode 13 and mode X. | VGA and VESA modes |
The RISC launches work into the drawing engines. A launch can finish before the drawing operation finishes. Later instructions stall when they require a busy engine or a shared resource. Issue time, result delay and register hazards are separate quantities; see instruction hazards.
The chip has two drawing modes. V1000 compatibility mode uses step, parallel draw and parameterized draw instructions. V2000 mode enables Triangle Engine register shadowing with DrawCtl[3:0] = 0xB. It uses tri in place of the compatibility draw instructions. DrawCtl controls this distinction.
Sources: Technical Spec, p.4, Technical Spec, p.5, Technical Spec, p.16, Technical Spec, p.21, Technical Spec, p.38, Technical Spec, p.63