Source Documents
Technical specification
V2200 3D/2D Graphics and Video Processor — Technical Spec, document 1159-001, ECN 0058, RevB 1/98. The supplied file has 69 pages. PDF page numbers and printed page numbers match.
| Pages | Subject |
|---|---|
| 4 | Block diagram |
| 5–24 | RISC instruction formats, registers, ISA, drawing and pipeline |
| 25–27 | Special RISC registers |
| 28–37 | Pixel Engine |
| 38–49 | PCI, native I/O, memory, CRTC and PLLs |
| 50 | DMA |
| 51–52 | Palette and cursor |
| 52–54 | Video input |
| 55 | Digital video output |
| 56 | Context switching |
| 57–60 | VGA |
| 61 | Reset |
| 62–68 | Pins, timing and electrical data |
| 69 | Mechanical drawing |
The PDF is the source for hardware statements on these pages. Extracted text is used for searching; the rendered PDF controls where extraction differs. Source issues lists conflicts and unresolved definitions.
Register conversion
The register catalogue is generated from the audited V2200 JSON conversion. It contains physical registers, constants, field aliases, indirect aliases, alternate views, palette entries, instruction formats and reset pin formats. Those entries are not added together as a physical register count.
Unspecified fields remain unspecified. Broad PCI Status/Command names do not acquire bit definitions from an unrelated standard. Optional Tex4Pal channel layouts are marked as derived; the documented view remains two sixteen-bit halves.
Source SHA-256:
12644cd50838923946ee5e5b60ec04498cdaa00c9bbdabd7f39d8e05ed75258e