Core Model

The workbench compiles the C core from Clara's renditionverite project to JavaScript with Emscripten. It runs the interpreter in a Web Worker. A synchronous mailbox adapter replaces host threads; submitted assembly does not execute on the server.

Cycle stepping advances the model to the next SClk edge. Instruction stepping continues until an instruction retires. The F, D, X1, X2 and W display uses the core's pipeline records. Fill, Triangle, Pixel and memory timing run through the same device model.

The initial board preset selects the core's 4 MiB reference SGRAM model, CL3, 100 MHz and closed-row scheduling. There is no board ROM. These are emulator settings, not measured V2200 timing.

Registers and instruction bytes follow the C model's byte order. Imported binaries are copied to the specified local-memory address. Framebuffer display reads that memory using the chosen pixel format and stride.

The assembler preserves the PDF instruction encodings. Known differences in the C decoder are shown beside the decoded instruction:

• pre reads its offset from bits 23:16 in the C core.
• The C core masks relative and absolute jump targets to 22 bits. The PDF describes a 24-bit field.
• Pipeline and memory timing follow the C implementation. The workbench is not a hardware timing measurement.

Datasheet conflicts are recorded separately. Rendition source references list the original driver files used by this wiki.

F7 steps an instruction. F8 steps a cycle. F9 runs or pauses. Ctrl+Enter assembles and loads the source. Breakpoints use byte addresses. Register and memory edits require paused execution.

The run limit bounds execution. Reset clears device state, retains the loaded memory and restarts at the program's entry address. Assemble & Load clears memory before loading a new program. The trace keeps the latest 256 records.