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--- tools:risc_model [2026/10/12 04:30] – external edit 127.0.0.1
+++ tools:risc_model [2026/10/12 04:57] (current) – external edit 127.0.0.1
@@ Line 33: / Line 33: @@
 Each cycle shows captured operands, forwarded values, pending results and committed register writes. Highlights use the C core's access events, including writes that store the same value. Held stages show their stall reason.
-Play cycles advances one SClk edge at a time. Fast Run samples the display while executing at full speed. The cycle history inspects recorded pipeline events; it leaves the device at its current state. The register bank is labelled Live registers, and editing is disabled while inspecting an earlier cycle.
+Play cycles records every SClk edge. At short intervals, it groups up to 16 edges per request and redraws at the screen's pace. Animations and memory inspection do not set the playback delay. Fast Run samples the display while executing at full speed. The cycle history inspects recorded pipeline events; it leaves the device at its current state. The register bank is labelled Live registers, and editing is disabled while inspecting an earlier cycle.
 Output stays above the pipeline. Pixels refresh after steps and stops. Recent committed register results remain visible after the program halts. Display settings select the local-memory range, pixel format and zoom; PNG export keeps the original pixel dimensions.
+Instruction fields start in hex, grouped at their encoded widths. Display can instead align them to DWORDs, WORDs or bytes, or show individual bits. Changing the view leaves the program and core state unchanged.