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RISC Workbench

Assemble and step the C RISC model. Execution, file imports and exports run in the browser.

Core model and limits. Worked examples.

Loading the RISC core…

Every edge · Fast Run samples the display.

Playback settings

Interval (ms) Cycle limit Animate transitions

PC — · Cycles 0 · Instructions 0 · Time 0 ns

Breakpoints and run limit

PC breakpoints Hex addresses, separated by commas or spaces. Run instruction limit

Output

Framebuffer

Zoom Framebuffer from local memory.

Framebuffer settings

Address Width Height Stride (bytes) Format

Committed registers

No committed writes.

Pipeline dataflow

No cycles captured yet.

Step a cycle to capture pipeline activity.

R Captured read · W Committed write · P Pending result · × Discarded result. Issue numbers identify instructions across stages.

Assembly

Example Origin

Source

Import files

Assembly file Binary file Binary address

Files are read in this browser. F7: instruction · F8: cycle · F9: run/pause · Ctrl+Enter: assemble.

Source at PC

No source loaded.

Pipeline latches

F	D	X1	X2	W
—	—	—	—	—

Disassembly

PC	Word	Instruction

Instruction fields

—

Field	Bits	Value

Live registers

Bank

Register	Hex value	Signed value

R marks a captured read; W marks an actual committed write, including an unchanged value. Yellow marks a changed value. Edits are not CPU writes.

Memory

Address

256 bytes. Edit a byte while execution is paused.

Trace

Records 0 records · last 256 retained

Cycle	Kind	PC	Instruction	Pipeline / stop