RISC Memory Access
The RISC uses big-endian byte order. Loads and stores calculate a byte address from S1 plus an unsigned 8-bit offset scaled by the transfer size.
| Transfer | Address | Alignment |
|---|---|---|
lb / sb | S1 + offset8 | Byte |
lh / sh | S1 + offset8 × 2 | Half-word |
lw / sw | S1 + offset8 × 4 | Word |
lv / lvra / sv | S1 + offset8 × 8 | Double-word; operand register pair must start at an even index |
pre | S1 + offset8 × 8 | Launches a prefetch |
lb and lh zero-extend their results. A vector load reads the even result at the starting address and the odd result four bytes later. lvra also prefetches the next eight-byte block. Store and load formats place the offset byte in different positions; see instruction formats.
sy, scr and scb store separate components into byte positions within YCrCb data. They leave the other bytes unchanged. scr and scb require quad-word alignment and take two cycles in DCache; their exact byte positions are in the opcode table.
Address regions
| RISC address | Region |
|---|---|
0x00000000..0x00FFFFFF | Up to 16 MB of local memory |
0xFFFE0000..0xFFFFFFFF | 128 KB BIOS ROM |
0xFFE00400 and above | Hardware control registers; use the detailed register addresses |
0xFFE00800..0xFFE00FFC | Pixel Engine state readback, at eight-byte intervals |
Fetch and relative control transfers do not increment across 0x00FFFFFF → 0x01000000 or 0xFFFFFFFF → 0. Absolute jumps select the target region explicitly.
The specification describes a line-buffer cache shared by RISC load data and PCI read data. pre, lvra and PCI reads to odd words launch an eight-byte prefetch; stores invalidate matching buffered data. The text distinguishes an eight-byte implementation from a planned sixteen-byte production block, so it does not establish one size for every chip revision.
Host and DMA byte swapping · Memory control
Sources: Technical Spec, p.5, Technical Spec, p.9, Technical Spec, p.10, Technical Spec, p.38