Memory Control

The memory interface supports SGRAM or SDRAM, clocked by MClk. Logic uses SClk; MClk must be at least SClk.

MemCtl selects memory type, latency, chip-bank configuration, speed and address swizzle. It is not changed by SoftReset. Several fields originate from MD reset straps. The source labels bits 4:2 “User defined,” but the reset table calls the matching strap MemSizeCS0; their function is left unresolved.

MemAdrSwizzle is zero for native operation and three for VGA. MemCtl also controls whether refresh or non-video accesses wait for blanking. Writing bits 23:16 sets refresh period value × 32 + 31 in MClk cycles; reading the same field returns the current counter. The register page distinguishes read and write interpretations.

MemDiag contains diagnostic disables, memory timing controls and StopRefresh. It is cleared by reset. MemCmd is named in the address map, but the supplied specification does not define its bit functions.

Fill write masking depends on memory type. SGRAM supports per-bit masks; SDRAM uses byte enables at mask bits 0, 8, 16 and 24. Fill programming describes this alternate register interpretation.

Sources: Technical Spec, p.21, Technical Spec, p.44, Technical Spec, p.45, Technical Spec, p.47, Technical Spec, p.61, Technical Spec, p.63