Branches and Jumps
Branches and jumps have one non-annulling delay slot: the instruction following the branch or jump always executes. halt and getpc have no delay slot. A delay slot cannot contain another branch or jump; it may contain halt or getpc.
| Instruction | Target / action |
|---|---|
bez, bnez, bgez, blz, bgz, blez | Test S1; target = delay-slot PC + sign-extended offset16 × 4. |
rjmp, rjmpl | Relative target = delay-slot PC + address × 4. rjmpl writes the link to ra. |
jmp, jmpl | Absolute target = address24 « 2. jmpl writes the link to ra. |
jmprl D,(S1) | Jump to S1; write the link to D. |
getpc D | Jump-never and link, using D. |
halt cause | Halt the RISC; cause is optional. |
Only blz and bgez are available when the S1 operand index is 63 or below. A shift result used for a branch decision has an interlocked delay of one.
Sequential fetch, relative branches and relative jumps do not cross the normal-memory / ROM boundary. An absolute jump can reach either region; its most significant address bit selects ROM when set. See RISC address space.
Sources: Technical Spec, p.5, Technical Spec, p.8, Technical Spec, p.11