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RISC Opcodes

OP occupies bits 31:24 of the 32-bit instruction. Select an opcode for operands, operation, hazards and its instruction format.

Opcode byte — high nibble rows, low nibble columns
OP	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
00	00add immediate	01sub immediate	02andn immediate	03subf immediate	04and immediate	05or immediate	06nor immediate	07xor immediate	08mul immediate	09mulsr8 immediate	0Amulsr16 immediate	0Bmulsr24 immediate	0Cmulsr32 immediate	0Dmulsr31 immediate	0Eclip immediate	0Ff2i immediate
10	10add	11sub	12andn	13subf	14and	15or	16nor	17xor	18mul	19mulsr8	1Amulsr16	1Bmulsr24	1Cmulsr32	1Dmulsr31	1Eclip	1Ff2i
20	20addv	21subv	22andnv	23subfv	24andv	25orv	26norv	27xorv	28mulv	29mulsr8v	2Amulsr16v	2Bmulsr24v	2Cmulsr32v	2Dmulsr31v	2Eclipv	2F—
30	30addvs	31subvs	32andnvs	33subfvs	34andvs	35orvs	36norvs	37xorvs	38mulvs	39mulsr8vs	3Amulsr16vs	3Bmulsr24vs	3Cmulsr32vs	3Dmulsr31vs	3Eclipvs	3F—
40	40addif	41subif	42seedsr immediate	43subfif	44rotr immediate	45sl immediate	46asr immediate	47sr immediate	48slt immediate	49sltu immediate	4Aseq immediate	4Baddsl8	4Cmin immediate	4Dmax immediate	4Esprii	4Fspri
50	50—	51—	52abs	53seedsr	54rotr	55sl	56asr	57sr	58slt	59sltu	5Aseq	5B—	5Cmin	5Dmax	5Eat	5Fspr
60	60bez	61bnez	62bgez	63blz	64bgz	65blez	66—	67—	68rjmp	69—	6Arjmpl	6Bgetpc	6Cjmp	6Dhalt	6Ejmpl	6Fjmprl
70	70lb	71lh	72lw	73pre	74lv	75lvra	76li	77lui	78sb	79sh	7Asw	7B—	7Csv	7Dsy	7Escr	7Fscb
80	80—	81—	82—	83—	84—	85—	86—	87—	88—	89—	8A—	8B—	8C—	8D—	8E—	8F—
90	90—	91—	92—	93—	94—	95—	96—	97—	98—	99—	9A—	9B—	9C—	9D—	9E—	9F—
A0	A0—	A1—	A2—	A3—	A4—	A5—	A6—	A7—	A8—	A9—	AA—	AB—	AC—	AD—	AE—	AF—
B0	B0—	B1—	B2—	B3—	B4—	B5—	B6—	B7—	B8—	B9—	BA—	BB—	BC—	BD—	BE—	BF—
C0	C0getxy	C1getyx	C2getra	C3getgb	C4sort	C5—	C6—	C7—	C8—	C9—	CA—	CB—	CC—	CD—	CE—	CF—
D0	D0step x/y	D1step q	D2step r/v	D3step i/u	D4step f	D5step g/b	D6step z/a	D7step cnt	D8stepv xy	D9stepv qu	DAstepv rv	DBstepv iv	DCstepv zv	DDstepv gb	DEstepv za	DFstepv cnt
E0	E0drawp	E1rdrawp	E2—	E3—	E4drawpxy	E5rdrawpxy	E6—	E7mbltfo	E8fill	E9mbrush	EAmblt	EBmbltf	ECcbrush8	EDcbrush16	EEcbrush32	EFcbltf
F0	F0draw1	F1rdraw1	F2draw2	F3rdraw2	F4—	F5—	F6—	F7—	F8draw3	F9rdraw3	FAdraw4	FBrdraw4	FCdraw5	FDrdraw5	FEtri	FF—

An empty cell has no definition in this specification.

Opcode Details

OP	Mnemonic	Operands	What it does	Timing
0x00	`add immediate`	`D,S2,uimm8`	D=S2+S1	result delay 0
0x01	`sub immediate`	`D,S2,uimm8`	D=S2-S1	result delay 0
0x02	`andn immediate`	`D,S2,uimm8`	D=S2 AND NOT S1	result delay 0
0x03	`subf immediate`	`D,S2,uimm8`	D=S1-S2	result delay 0
0x04	`and immediate`	`D,S2,uimm8`	D=S2 AND S1	result delay 0
0x05	`or immediate`	`D,S2,uimm8`	D=S2 OR S1	result delay 0
0x06	`nor immediate`	`D,S2,uimm8`	D=S2 NOR S1	result delay 0
0x07	`xor immediate`	`D,S2,uimm8`	D=S2 XOR S1	result delay 0
0x08	`mul immediate`	`D,S2,uimm8`	D=low32(S2*S1)	1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles
0x09	`mulsr8 immediate`	`D,S2,uimm8`