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| risc:opcodes [2026/10/11 22:55] – created - external edit 127.0.0.1 | risc:opcodes [2026/10/11 23:17] (current) – external edit 127.0.0.1 |
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| ===== Opcode Details ===== | ===== Opcode Details ===== |
| |
| ^ OP ^ Mnemonic ^ Operands ^ What it does ^ Timing ^ | ~~OPCODEDETAILS~~ |
| | [[risc:opcode:00|0x00]] | ''add immediate'' | ''D,S2,uimm8'' | D=S2+S1 | result delay 0 | | |
| | [[risc:opcode:01|0x01]] | ''sub immediate'' | ''D,S2,uimm8'' | D=S2-S1 | result delay 0 | | |
| | [[risc:opcode:02|0x02]] | ''andn immediate'' | ''D,S2,uimm8'' | D=S2 AND NOT S1 | result delay 0 | | |
| | [[risc:opcode:03|0x03]] | ''subf immediate'' | ''D,S2,uimm8'' | D=S1-S2 | result delay 0 | | |
| | [[risc:opcode:04|0x04]] | ''and immediate'' | ''D,S2,uimm8'' | D=S2 AND S1 | result delay 0 | | |
| | [[risc:opcode:05|0x05]] | ''or immediate'' | ''D,S2,uimm8'' | D=S2 OR S1 | result delay 0 | | |
| | [[risc:opcode:06|0x06]] | ''nor immediate'' | ''D,S2,uimm8'' | D=S2 NOR S1 | result delay 0 | | |
| | [[risc:opcode:07|0x07]] | ''xor immediate'' | ''D,S2,uimm8'' | D=S2 XOR S1 | result delay 0 | | |
| | [[risc:opcode:08|0x08]] | ''mul immediate'' | ''D,S2,uimm8'' | D=low32(S2*S1) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:09|0x09]] | ''mulsr8 immediate'' | ''D,S2,uimm8'' | D=low32((S2*S1)>>8) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:0a|0x0A]] | ''mulsr16 immediate'' | ''D,S2,uimm8'' | D=low32((S2*S1)>>16) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:0b|0x0B]] | ''mulsr24 immediate'' | ''D,S2,uimm8'' | D=low32((S2*S1)>>24) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:0c|0x0C]] | ''mulsr32 immediate'' | ''D,S2,uimm8'' | D=low32((S2*S1)>>32) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:0d|0x0D]] | ''mulsr31 immediate'' | ''D,S2,uimm8'' | D=low32((S2*S1)>>31) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:0e|0x0E]] | ''clip immediate'' | ''S2,uimm8'' | Clip=(Clip<<1)&0xfc %%|%% ((signed(S2-S1)>0)?4:0) | Clip read hazard 1 | | |
| | [[risc:opcode:0f|0x0F]] | ''f2i immediate'' | ''D,S2,uimm8'' | Convert IEEE754 S2 * 2^S1, floor toward -infinity, saturate; 0<=S1<=30 | result delay 0 | | |
| | [[risc:opcode:10|0x10]] | ''add'' | ''D,S2,S1'' | D=S2+S1 | result delay 0 | | |
| | [[risc:opcode:11|0x11]] | ''sub'' | ''D,S2,S1'' | D=S2-S1 | result delay 0 | | |
| | [[risc:opcode:12|0x12]] | ''andn'' | ''D,S2,S1'' | D=S2 AND NOT S1 | result delay 0 | | |
| | [[risc:opcode:13|0x13]] | ''subf'' | ''D,S2,S1'' | D=S1-S2 | result delay 0 | | |
| | [[risc:opcode:14|0x14]] | ''and'' | ''D,S2,S1'' | D=S2 AND S1 | result delay 0 | | |
| | [[risc:opcode:15|0x15]] | ''or'' | ''D,S2,S1'' | D=S2 OR S1 | result delay 0 | | |
| | [[risc:opcode:16|0x16]] | ''nor'' | ''D,S2,S1'' | D=S2 NOR S1 | result delay 0 | | |
| | [[risc:opcode:17|0x17]] | ''xor'' | ''D,S2,S1'' | D=S2 XOR S1 | result delay 0 | | |
| | [[risc:opcode:18|0x18]] | ''mul'' | ''D,S2,S1'' | D=low32(S2*S1) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:19|0x19]] | ''mulsr8'' | ''D,S2,S1'' | D=low32((S2*S1)>>8) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:1a|0x1A]] | ''mulsr16'' | ''D,S2,S1'' | D=low32((S2*S1)>>16) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:1b|0x1B]] | ''mulsr24'' | ''D,S2,S1'' | D=low32((S2*S1)>>24) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:1c|0x1C]] | ''mulsr32'' | ''D,S2,S1'' | D=low32((S2*S1)>>32) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:1d|0x1D]] | ''mulsr31'' | ''D,S2,S1'' | D=low32((S2*S1)>>31) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:1e|0x1E]] | ''clip'' | ''S2,S1'' | Clip=(Clip<<1)&0xfc %%|%% ((signed(S2-S1)>0)?4:0) | Clip read hazard 1 | | |
| | [[risc:opcode:1f|0x1F]] | ''f2i'' | ''D,S2,S1'' | Convert IEEE754 S2 * 2^S1, floor toward -infinity, saturate; 0<=S1<=30 | result delay 0 | | |
| | [[risc:opcode:20|0x20]] | ''addv'' | ''D,S2,S1'' | D=S2+S1 | result delay 0 | | |
| | [[risc:opcode:21|0x21]] | ''subv'' | ''D,S2,S1'' | D=S2-S1 | result delay 0 | | |
| | [[risc:opcode:22|0x22]] | ''andnv'' | ''D,S2,S1'' | D=S2 AND NOT S1 | result delay 0 | | |
| | [[risc:opcode:23|0x23]] | ''subfv'' | ''D,S2,S1'' | D=S1-S2 | result delay 0 | | |
| | [[risc:opcode:24|0x24]] | ''andv'' | ''D,S2,S1'' | D=S2 AND S1 | result delay 0 | | |
| | [[risc:opcode:25|0x25]] | ''orv'' | ''D,S2,S1'' | D=S2 OR S1 | result delay 0 | | |
| | [[risc:opcode:26|0x26]] | ''norv'' | ''D,S2,S1'' | D=S2 NOR S1 | result delay 0 | | |
| | [[risc:opcode:27|0x27]] | ''xorv'' | ''D,S2,S1'' | D=S2 XOR S1 | result delay 0 | | |
| | [[risc:opcode:28|0x28]] | ''mulv'' | ''D,S2,S1'' | D=low32(S2*S1) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:29|0x29]] | ''mulsr8v'' | ''D,S2,S1'' | D=low32((S2*S1)>>8) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:2a|0x2A]] | ''mulsr16v'' | ''D,S2,S1'' | D=low32((S2*S1)>>16) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:2b|0x2B]] | ''mulsr24v'' | ''D,S2,S1'' | D=low32((S2*S1)>>24) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:2c|0x2C]] | ''mulsr32v'' | ''D,S2,S1'' | D=low32((S2*S1)>>32) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:2d|0x2D]] | ''mulsr31v'' | ''D,S2,S1'' | D=low32((S2*S1)>>31) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:2e|0x2E]] | ''clipv'' | ''S2,S1'' | Clip=(Clip<<1)&0xfc %%|%% ((signed(S2-S1)>0)?4:0) | Clip read hazard 1 | | |
| | [[risc:opcode:30|0x30]] | ''addvs'' | ''D,S2,S1'' | D=S2+S1 | result delay 0 | | |
| | [[risc:opcode:31|0x31]] | ''subvs'' | ''D,S2,S1'' | D=S2-S1 | result delay 0 | | |
| | [[risc:opcode:32|0x32]] | ''andnvs'' | ''D,S2,S1'' | D=S2 AND NOT S1 | result delay 0 | | |
| | [[risc:opcode:33|0x33]] | ''subfvs'' | ''D,S2,S1'' | D=S1-S2 | result delay 0 | | |
| | [[risc:opcode:34|0x34]] | ''andvs'' | ''D,S2,S1'' | D=S2 AND S1 | result delay 0 | | |
| | [[risc:opcode:35|0x35]] | ''orvs'' | ''D,S2,S1'' | D=S2 OR S1 | result delay 0 | | |
| | [[risc:opcode:36|0x36]] | ''norvs'' | ''D,S2,S1'' | D=S2 NOR S1 | result delay 0 | | |
| | [[risc:opcode:37|0x37]] | ''xorvs'' | ''D,S2,S1'' | D=S2 XOR S1 | result delay 0 | | |
| | [[risc:opcode:38|0x38]] | ''mulvs'' | ''D,S2,S1'' | D=low32(S2*S1) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:39|0x39]] | ''mulsr8vs'' | ''D,S2,S1'' | D=low32((S2*S1)>>8) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:3a|0x3A]] | ''mulsr16vs'' | ''D,S2,S1'' | D=low32((S2*S1)>>16) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:3b|0x3B]] | ''mulsr24vs'' | ''D,S2,S1'' | D=low32((S2*S1)>>24) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:3c|0x3C]] | ''mulsr32vs'' | ''D,S2,S1'' | D=low32((S2*S1)>>32) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:3d|0x3D]] | ''mulsr31vs'' | ''D,S2,S1'' | D=low32((S2*S1)>>31) | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | |
| | [[risc:opcode:3e|0x3E]] | ''clipvs'' | ''S2,S1'' | Clip=(Clip<<1)&0xfc %%|%% ((signed(S2-S1)>0)?4:0) | Clip read hazard 1 | | |
| | [[risc:opcode:40|0x40]] | ''addif'' | ''D,S2,uimm8'' | D=S2+(uimm8<<16) | 0 | | |
| | [[risc:opcode:41|0x41]] | ''subif'' | ''D,S2,uimm8'' | D=S2-(uimm8<<16) | 0 | | |
| | [[risc:opcode:42|0x42]] | ''seedsr immediate'' | ''D,S2,uimm8'' | Same seedsr operation with immediate S1. | 2 | | |
| | [[risc:opcode:43|0x43]] | ''subfif'' | ''D,S2,uimm8'' | D=(uimm8<<16)-S2 | 0 | | |
| | [[risc:opcode:44|0x44]] | ''rotr immediate'' | ''D,S2,uimm8'' | Rotate S2 right by S1. | 0; branch-decision result interlock 1 | | |
| | [[risc:opcode:45|0x45]] | ''sl immediate'' | ''D,S2,uimm8'' | Logical shift left by S1&31. | 0; branch interlock 1 | | |
| | [[risc:opcode:46|0x46]] | ''asr immediate'' | ''D,S2,uimm8'' | Arithmetic shift right by S1&31. | 0; branch interlock 1 | | |
| | [[risc:opcode:47|0x47]] | ''sr immediate'' | ''D,S2,uimm8'' | Logical shift right by S1&31. | 0; branch interlock 1 | | |
| | [[risc:opcode:48|0x48]] | ''slt immediate'' | ''D,S2,uimm8'' | D=(signed(S2)<signed(S1)) ? 1 : 0 | 0 | | |
| | [[risc:opcode:49|0x49]] | ''sltu immediate'' | ''D,S2,uimm8'' | Unsigned comparison. | 0 | | |
| | [[risc:opcode:4a|0x4A]] | ''seq immediate'' | ''D,S2,uimm8'' | D=(S2==S1) ? 1 : 0 | 0 | | |
| | [[risc:opcode:4b|0x4B]] | ''addsl8'' | ''D,S2,uimm8'' | D=S2+(uimm8<<8) | 0 | | |
| | [[risc:opcode:4c|0x4C]] | ''min immediate'' | ''D,S2,uimm8'' | D=min(S2,S1) | 0 | | |
| | [[risc:opcode:4d|0x4D]] | ''max immediate'' | ''D,S2,uimm8'' | D=max(S2,S1) | 0 | | |
| | [[risc:opcode:4e|0x4E]] | ''sprii'' | ''reg,immed16'' | PixRegSpecifiedBy(reg)=immed16 | Triangle shadow destination -> spr hazard 2 | | |
| | [[risc:opcode:4f|0x4F]] | ''spri'' | ''reg,S2'' | PixRegSpecifiedBy(reg)=S2 | Triangle shadow destination -> spr hazard 2 | | |
| | [[risc:opcode:52|0x52]] | ''abs'' | ''D,S1'' | D=abs(S1) | 0 | | |
| | [[risc:opcode:53|0x53]] | ''seedsr'' | ''D,S2,S1'' | D=seed(S2)>>(scale(S2)-S1); shift range 0..30. Updates seed, scale, index. See fill hazard. | 2 | | |
| | [[risc:opcode:54|0x54]] | ''rotr'' | ''D,S2,S1'' | Rotate S2 right by S1. | 0; branch-decision result interlock 1 | | |
| | [[risc:opcode:55|0x55]] | ''sl'' | ''D,S2,S1'' | Logical shift left by S1&31. | 0; branch interlock 1 | | |
| | [[risc:opcode:56|0x56]] | ''asr'' | ''D,S2,S1'' | Arithmetic shift right by S1&31. | 0; branch interlock 1 | | |
| | [[risc:opcode:57|0x57]] | ''sr'' | ''D,S2,S1'' | Logical shift right by S1&31. | 0; branch interlock 1 | | |
| | [[risc:opcode:58|0x58]] | ''slt'' | ''D,S2,S1'' | D=(signed(S2)<signed(S1)) ? 1 : 0 | 0 | | |
| | [[risc:opcode:59|0x59]] | ''sltu'' | ''D,S2,S1'' | Unsigned comparison. | 0 | | |
| | [[risc:opcode:5a|0x5A]] | ''seq'' | ''D,S2,S1'' | D=(S2==S1) ? 1 : 0 | 0 | | |
| | [[risc:opcode:5c|0x5C]] | ''min'' | ''D,S2,S1'' | D=min(S2,S1) | 0 | | |
| | [[risc:opcode:5d|0x5D]] | ''max'' | ''D,S2,S1'' | D=max(S2,S1) | 0 | | |
| | [[risc:opcode:5e|0x5E]] | ''at'' | ''D,S2,S1'' | D=(S2+S1)&0xffff0000 | 0 | | |
| | [[risc:opcode:5f|0x5F]] | ''spr'' | ''(S1),S2'' | PixRegSpecifiedBy(S1)=S2 | Triangle shadow destination -> spr hazard 2 | | |
| | [[risc:opcode:60|0x60]] | ''bez'' | ''S1,offset16'' | If S1==0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported. | one non-annulling delay slot | | |
| | [[risc:opcode:61|0x61]] | ''bnez'' | ''S1,offset16'' | If S1!=0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported. | one non-annulling delay slot | | |
| | [[risc:opcode:62|0x62]] | ''bgez'' | ''S1,offset16'' | If S1>=0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported. | one non-annulling delay slot | | |
| | [[risc:opcode:63|0x63]] | ''blz'' | ''S1,offset16'' | If S1<0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported. | one non-annulling delay slot | | |
| | [[risc:opcode:64|0x64]] | ''bgz'' | ''S1,offset16'' | If S1>0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported. | one non-annulling delay slot | | |
| | [[risc:opcode:65|0x65]] | ''blez'' | ''S1,offset16'' | If S1<=0, branch to delay-slot PC + sign-extended(offset16*4). For operand indices <=63 only bgez/blz supported. | one non-annulling delay slot | | |
| | [[risc:opcode:68|0x68]] | ''rjmp'' | ''addr'' | Relative jump to delay-slot PC+addr*4 | one non-annulling delay slot | | |
| | [[risc:opcode:6a|0x6A]] | ''rjmpl'' | ''addr'' | Relative jump and link in ra | one non-annulling delay slot | | |
| | [[risc:opcode:6b|0x6B]] | ''getpc'' | ''D'' | Jump never, link in D | no delay slot | | |
| | [[risc:opcode:6c|0x6C]] | ''jmp'' | ''addr24'' | Absolute jump to addr24<<2; MSB selects ROM | one non-annulling delay slot | | |
| | [[risc:opcode:6d|0x6D]] | ''halt'' | ''cause'' | Halt RISC; optional cause; last executed instruction | no delay slot | | |
| | [[risc:opcode:6e|0x6E]] | ''jmpl'' | ''addr24'' | Absolute jump and link in ra | one non-annulling delay slot | | |
| | [[risc:opcode:6f|0x6F]] | ''jmprl'' | ''D,(S1)'' | Jump to S1 and link in D | one non-annulling delay slot | | |
| | [[risc:opcode:70|0x70]] | ''lb'' | ''D,offset8(S1)'' | Unsigned byte load; address=S1+offset8 | load interlock 1; pre/li/lui 0 | | |
| | [[risc:opcode:71|0x71]] | ''lh'' | ''D,offset8(S1)'' | Unsigned halfword load; address=S1+offset8*2; halfword aligned | load interlock 1; pre/li/lui 0 | | |
| | [[risc:opcode:72|0x72]] | ''lw'' | ''D,offset8(S1)'' | Word load; address=S1+offset8*4; word aligned | load interlock 1; pre/li/lui 0 | | |
| | [[risc:opcode:73|0x73]] | ''pre'' | ''offset8(S1)'' | Prefetch S1+offset8*8 | load interlock 1; pre/li/lui 0 | | |
| | [[risc:opcode:74|0x74]] | ''lv'' | ''D,offset8(S1)'' | Load even/odd pair at S1+offset8*8; double-word aligned | load interlock 1; pre/li/lui 0 | | |
| | [[risc:opcode:75|0x75]] | ''lvra'' | ''D,offset8(S1)'' | Vector load plus prefetch next double word | load interlock 1; pre/li/lui 0 | | |
| | [[risc:opcode:76|0x76]] | ''li'' | ''D,immed16'' | D=unsigned immed16 | load interlock 1; pre/li/lui 0 | | |
| | [[risc:opcode:77|0x77]] | ''lui'' | ''D,immed16'' | D=immed16<<16 | load interlock 1; pre/li/lui 0 | | |
| | [[risc:opcode:78|0x78]] | ''sb'' | ''offset8(S1),S2'' | Byte store at S1+offset8 | — | | |
| | [[risc:opcode:79|0x79]] | ''sh'' | ''offset8(S1),S2'' | Halfword store at S1+offset8*2 | — | | |
| | [[risc:opcode:7a|0x7A]] | ''sw'' | ''offset8(S1),S2'' | Word store at S1+offset8*4 | — | | |
| | [[risc:opcode:7c|0x7C]] | ''sv'' | ''offset8(S1),S2'' | Store even/odd pair at S1+offset8*8; double-word aligned | — | | |
| | [[risc:opcode:7d|0x7D]] | ''sy'' | ''offset8(S1),S2'' | Store S2 bytes at offsets 0,2,4,6 from S1+offset8*8; other bytes unchanged | — | | |
| | [[risc:opcode:7e|0x7E]] | ''scr'' | ''offset8(S1),S2'' | Store S2 bytes at offsets 1,5,9,13; quad-word aligned | scr takes two DCache cycles | | |
| | [[risc:opcode:7f|0x7F]] | ''scb'' | ''offset8(S1),S2'' | Store S2 bytes at offsets 3,7,11,15 from S1+offset8*8; quad-word aligned; other bytes unchanged. | two DCache cycles | | |
| | [[risc:opcode:c0|0xC0]] | ''getxy'' | ''D,S1'' | Deven=S1&0xffff0000; Dodd=S1<<16 | 0 | | |
| | [[risc:opcode:c1|0xC1]] | ''getyx'' | ''D,S1'' | Deven=S1<<16; Dodd=S1&0xffff0000 | 0 | | |
| | [[risc:opcode:c2|0xC2]] | ''getra'' | ''D,S1'' | D0=S1&0xff0000; D1=(S1>>8)&0xff0000 | 0 | | |
| | [[risc:opcode:c3|0xC3]] | ''getgb'' | ''D,S1'' | D0=(S1<<8)&0xff0000; D1=(S1<<16)&0xff0000 | 0 | | |
| | [[risc:opcode:c4|0xC4]] | ''sort'' | ''S3,S2,S1'' | Sorts register indices into Seg0/1/2 by values. Ties: S1 smallest then S2. Shifts four identical flags into Clip based on ceil(max)-1 < ceil(min). | 2 cycles; Seg hazard 3, Clip hazard 2 | | |
| | [[risc:opcode:d0|0xD0]] | ''step x/y'' | ''D,S2,S1'' | Even S2 updates XShadow and XDir from sign(S1); odd S2 updates Y. 16I.16F. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d1|0xD1]] | ''step q'' | ''D,S2,S1'' | Seed operation; Q 0I.24F. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d2|0xD2]] | ''step r/v'' | ''D,S2,S1'' | Even S2 updates R; odd updates V and VDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d3|0xD3]] | ''step i/u'' | ''D,S2,S1'' | Even updates R=G=B=intensity; odd updates U and UDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d4|0xD4]] | ''step f'' | ''D,S2,S1'' | Odd S2 updates fog factor. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d5|0xD5]] | ''step g/b'' | ''D,S2,S1'' | Even updates G; odd updates B. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d6|0xD6]] | ''step z/a'' | ''D,S2,S1'' | Even updates Z 21I.11F; odd Alpha 16I.16F. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d7|0xD7]] | ''step cnt'' | ''D,S2,S1'' | Even S2 updates Count from bits31:16. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d8|0xD8]] | ''stepv xy'' | ''D,S2,S1'' | Vector XShadow/XDir and Y. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:d9|0xD9]] | ''stepv qu'' | ''D,S2,S1'' | Vector Q seed and U/UDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:da|0xDA]] | ''stepv rv'' | ''D,S2,S1'' | Vector R and V/VDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:db|0xDB]] | ''stepv iv'' | ''D,S2,S1'' | Vector RGB intensity and V/VDir. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:dc|0xDC]] | ''stepv zv'' | ''D,S2,S1'' | Vector Z 21I.11F and V 16I.16F. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:dd|0xDD]] | ''stepv gb'' | ''D,S2,S1'' | Vector G and B. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:de|0xDE]] | ''stepv za'' | ''D,S2,S1'' | Vector Z and Alpha. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:df|0xDF]] | ''stepv cnt'' | ''D,S2,S1'' | Vector Count; extra odd add. Also adds operands into RISC destination. Illegal when DrawCtl[3:0]=11. Other color/coordinate formats 16I.16F. | Count -> draw hazard 1; XShadow -> parallel draw hazard 1; triangle shadow destination -> step hazard 2 | | |
| | [[risc:opcode:e0|0xE0]] | ''drawp'' | ''D,S2,S1'' | Single parallel draw; update XShadow and U. Unsigned Count. Parallel pixels/cycle = 4/sizeof(pixel). SwapUV must be zero, masks all ones, clamps disabled. | Count or XShadow setup hazard 1; DrawCtl hazard 3 | | |
| | [[risc:opcode:e1|0xE1]] | ''rdrawp'' | ''D,S2,S1'' | Repeated parallel draw; update XShadow and U. Unsigned Count. Parallel pixels/cycle = 4/sizeof(pixel). SwapUV must be zero, masks all ones, clamps disabled. | Count or XShadow setup hazard 1; DrawCtl hazard 3 | | |
| | [[risc:opcode:e4|0xE4]] | ''drawpxy'' | ''D,S2,S1'' | Single resetting parallel draw. Unsigned Count. Parallel pixels/cycle = 4/sizeof(pixel). SwapUV must be zero, masks all ones, clamps disabled. | Count or XShadow setup hazard 1; DrawCtl hazard 3 | | |
| | [[risc:opcode:e5|0xE5]] | ''rdrawpxy'' | ''D,S2,S1'' | Repeated resetting parallel draw. Unsigned Count. Parallel pixels/cycle = 4/sizeof(pixel). SwapUV must be zero, masks all ones, clamps disabled. | Count or XShadow setup hazard 1; DrawCtl hazard 3 | | |
| | [[risc:opcode:e7|0xE7]] | ''mbltfo'' | ''D,S2,S1'' | Opaque monochrome FIFO BitBlt. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:e8|0xE8]] | ''fill'' | ''D,S2,S1'' | Solid color fill. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:e9|0xE9]] | ''mbrush'' | ''D,S2,S1'' | Transparent monochrome brush. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:ea|0xEA]] | ''mblt'' | ''D,S2,S1'' | Transparent monochrome BitBlt using a8-a15. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:eb|0xEB]] | ''mbltf'' | ''D,S2,S1'' | Transparent monochrome FIFO BitBlt. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:ec|0xEC]] | ''cbrush8'' | ''D,S2,S1'' | Eight-pixel color brush. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:ed|0xED]] | ''cbrush16'' | ''D,S2,S1'' | Sixteen-pixel color brush. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:ee|0xEE]] | ''cbrush32'' | ''D,S2,S1'' | Thirty-two-pixel color brush. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:ef|0xEF]] | ''cbltf'' | ''D,S2,S1'' | Color FIFO BitBlt; format bit7 enables chroma key. S2 even=byte address, odd=pixel length; D receives next address S2+S1. FIFO cannot be RISC operand. Length 1..1984 except mblt 1..255. | 1-cycle launch except possible mblt/cbrush startup; a0/a3/a8-a15 hazard 3, a1 hazard 1, a2 hazard 2; fill -> seed hazard 3 | | |
| | [[risc:opcode:f0|0xF0]] | ''draw1'' | ''D,S2,S1'' | 1 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:f1|0xF1]] | ''rdraw1'' | ''D,S2,S1'' | 1 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:f2|0xF2]] | ''draw2'' | ''D,S2,S1'' | 2 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:f3|0xF3]] | ''rdraw2'' | ''D,S2,S1'' | 2 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:f8|0xF8]] | ''draw3'' | ''D,S2,S1'' | 3 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:f9|0xF9]] | ''rdraw3'' | ''D,S2,S1'' | 3 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:fa|0xFA]] | ''draw4'' | ''D,S2,S1'' | 4 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:fb|0xFB]] | ''rdraw4'' | ''D,S2,S1'' | 4 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:fc|0xFC]] | ''draw5'' | ''D,S2,S1'' | 5 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:fd|0xFD]] | ''rdraw5'' | ''D,S2,S1'' | 5 parameter pairs selected by DrawCtl; pair5 adds G/B. Signed Count; no draw for Count<=0. Perspective-correct variants require >=2 pairs and preceding step q. | source says draw takes 3 cycles but also gives launch=2+2*ParamPairs; rdraw=2+2*ParamPairs+pixels. See DRAW_TIMING | | |
| | [[risc:opcode:fe|0xFE]] | ''tri'' | ''D,S2,S1'' | Launch triangle; prelaunch vector add can update xy,zq,uv,ra,gb,r2f,g2b2. DrawCtl[3:0]=0xB; shadowed registers and DrawCtl writes stall while triangle busy. | 1-cycle launch; total=4+scanlines+pixels excluding memory stalls; tri -> fill hazard 3 | | |
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