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Rendition Vérité V2200

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risc:alu [2026/10/11 23:17] – created - external edit 127.0.0.1risc:alu [2026/10/11 23:23] (current) – external edit 127.0.0.1
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 | mul, mulsr8/16/24/31/32 | Signed 32×32 product, optionally shifted right before selecting low 32 result bits | | mul, mulsr8/16/24/31/32 | Signed 32×32 product, optionally shifted right before selecting low 32 result bits |
 | clip | Signed comparison S2−S1 > 0; shift its result into Clip | | clip | Signed comparison S2−S1 > 0; shift its result into Clip |
-| f2i | Convert IEEE 754 float S2 to integer after scaling by 2^S1 |+| f2i | Convert IEEE 754 float S2 to integer after scaling by 2<sup>S1</sup> |
 | slt, sltu, seq | Signed less-than, unsigned less-than, equality | | slt, sltu, seq | Signed less-than, unsigned less-than, equality |
 | min, max, abs | Signed minimum, maximum and absolute value | | min, max, abs | Signed minimum, maximum and absolute value |
risc/alu.txt · Last modified: by 127.0.0.1