Differences
This shows you the differences between two versions of the page.
| video:clocks [2026/10/11 23:02] – created - external edit 127.0.0.1 | video:clocks [2026/10/11 23:17] (current) – external edit 127.0.0.1 | ||
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| When digital video output is enabled, ExtraDiv2 supplies an additional divide-by-two before PClk. VOutClk uses the preceding divider output, twice the pixel rate. For a 31.5 MHz pixel rate the source example uses a 126 MHz oscillator, P = 2 and ExtraDiv2 enabled. | When digital video output is enabled, ExtraDiv2 supplies an additional divide-by-two before PClk. VOutClk uses the preceding divider output, twice the pixel rate. For a 31.5 MHz pixel rate the source example uses a 126 MHz oscillator, P = 2 and ExtraDiv2 enabled. | ||
| - | The PDF lists default PLL settings for each combination of maximum memory and RISC clock straps. Those exact startup values are in [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | The PDF lists default PLL settings for each combination of maximum memory and RISC clock straps. Those exact startup values are in [[https://verite.3d32.org/ |
| [[video: | [[video: | ||
| - | Sources: [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | Sources: [[https://verite.3d32.org/ |