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Rendition Vérité V2200

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risc:opcode:0d [2026/10/11 22:55] – created - external edit 127.0.0.1risc:opcode:0d [2026/10/11 23:17] (current) – external edit 127.0.0.1
Line 6: Line 6:
 | OP | ''0x0D'' | | OP | ''0x0D'' |
 | Operands | ''D,S2,uimm8'' | | Operands | ''D,S2,uimm8'' |
-| Operation | D=low32((S2*S1)>>31) |+| Operation | D=low32%%((%%S2*S1)%%>>%%31) |
 | Timing | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles | | Timing | 1-cycle result delay for scalar multiply; vector even result delay 0, odd 1; vectors launch in 2 cycles |
  
 [[risc:hazards|Instruction hazards]] · [[registers:opcodes:start|Instruction formats]] [[risc:hazards|Instruction hazards]] · [[registers:opcodes:start|Instruction formats]]
  
-Source: [[this>lib/exe/fetch.php?media=source:v2200spec.pdf#page=8|Technical Spec, p.8]]+Source: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=8|Technical Spec, p.8]]
  
risc/opcode/0d.1791759349.txt.gz · Last modified: by 127.0.0.1