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Rendition Vérité V2200

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hardware:timing [2026/10/11 23:02] – created - external edit 127.0.0.1hardware:timing [2026/10/11 23:17] (current) – external edit 127.0.0.1
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 | tch | Control/address hold | 2.6 | 1.6 | | tch | Control/address hold | 2.6 | 1.6 |
  
-Source waveform: [[this>lib/exe/fetch.php?media=source:v2200spec.pdf#page=63|Technical Spec, p.63]]+Source waveform: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=63|Technical Spec, p.63]]
  
 ===== Memory Read ===== ===== Memory Read =====
Line 26: Line 26:
 The figure caption on page 64 says memory write, but its table and signals describe memory read. The figure caption on page 64 says memory write, but its table and signals describe memory read.
  
-Source waveform: [[this>lib/exe/fetch.php?media=source:v2200spec.pdf#page=64|Technical Spec, p.64]]+Source waveform: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=64|Technical Spec, p.64]]
  
 ===== Video Input ===== ===== Video Input =====
Line 34: Line 34:
 | tvh | Hold for those signals after VInClk | 0.0 ns | | tvh | Hold for those signals after VInClk | 0.0 ns |
  
-Source waveform: [[this>lib/exe/fetch.php?media=source:v2200spec.pdf#page=65|Technical Spec, p.65]]+Source waveform: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=65|Technical Spec, p.65]]
  
 ===== XBus ===== ===== XBus =====
Line 49: Line 49:
 | txp | Minimum precharge between accesses | 3 × BClk − 3 | | txp | Minimum precharge between accesses | 3 × BClk − 3 |
  
-Source waveform: [[this>lib/exe/fetch.php?media=source:v2200spec.pdf#page=66|Technical Spec, p.66]]+Source waveform: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=66|Technical Spec, p.66]]
  
 [[hardware:interfaces|PCI timing and interface signals]] · [[hardware:electrical|Electrical characteristics]] [[hardware:interfaces|PCI timing and interface signals]] · [[hardware:electrical|Electrical characteristics]]
  
hardware/timing.1791759777.txt.gz · Last modified: by 127.0.0.1