Differences
This shows you the differences between two versions of the page.
| hardware:interfaces [2026/10/11 23:02] – created - external edit 127.0.0.1 | hardware:interfaces [2026/10/11 23:17] (current) – external edit 127.0.0.1 | ||
|---|---|---|---|
| Line 2: | Line 2: | ||
| ^ Interface ^ Signals / width ^ Source ^ | ^ Interface ^ Signals / width ^ Source ^ | ||
| - | | PCI | AD[31:0], C/BE[3:0]#, Frame#, IRdy#, TRdy#, Stop#, parity and arbitration | [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | | PCI | AD[31:0], C/BE[3:0]#, Frame#, IRdy#, TRdy#, Stop#, parity and arbitration | [[https://verite.3d32.org/ |
| - | | Memory | MD[63:0], MA[11:0], two chip selects, eight byte masks, memory command signals and clocks | [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | | Memory | MD[63:0], MA[11:0], two chip selects, eight byte masks, memory command signals and clocks | [[https://verite.3d32.org/ |
| - | | ROM | RD[7:0], RA[16:0], ROMOE#, ROMWE#, ROMCS#; shares memory data pins | [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | | ROM | RD[7:0], RA[16:0], ROMOE#, ROMWE#, ROMCS#; shares memory data pins | [[https://verite.3d32.org/ |
| - | | Video input | Eight-bit data plus Active, VBlank, HSync, VSync and VInClk | [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | | Video input | Eight-bit data plus Active, VBlank, HSync, VSync and VInClk | [[https://verite.3d32.org/ |
| - | | Video output | Analog RGB, sync, DDC; byte-serial digital output on XD[7:0] | [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | | Video output | Analog RGB, sync, DDC; byte-serial digital output on XD[7:0] | [[https://verite.3d32.org/ |
| - | | XBus | XD[7:0], XA[3:0], read/write strobes, wait, interrupt and reset | [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | | XBus | XD[7:0], XA[3:0], read/write strobes, wait, interrupt and reset | [[https://verite.3d32.org/ |
| XBus exposes a sixteen-byte external-device window at native I/O +0xF0..+0xFF. Host byte, half-word and word operations become one, two and four external byte accesses, beginning at the lowest address. TestMode must be disabled when using XBus, VIn or VOut. | XBus exposes a sixteen-byte external-device window at native I/O +0xF0..+0xFF. Host byte, half-word and word operations become one, two and four external byte accesses, beginning at the lowest address. TestMode must be disabled when using XBus, VIn or VOut. | ||
| Line 29: | Line 29: | ||
| Digital and analog supplies are 3.135..3.465 V. The V5V latch-up supply is 4.75..5.25 V. XtalIn is not five-volt tolerant. The source recommends a separate 3.3 V analog regulator for DAC/PLL isolation. | Digital and analog supplies are 3.135..3.465 V. The V5V latch-up supply is 4.75..5.25 V. XtalIn is not five-volt tolerant. The source recommends a separate 3.3 V analog regulator for DAC/PLL isolation. | ||
| - | The package drawing gives a 27.00 mm outline, 1.27 mm pitch and 320 solder-resist openings. [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | The package drawing gives a 27.00 mm outline, 1.27 mm pitch and 320 solder-resist openings. [[https://verite.3d32.org/ |
| - | Sources: [[this>lib/exe/fetch.php?media=source:v2200spec.pdf# | + | Sources: [[https://verite.3d32.org/ |
| [[hardware: | [[hardware: | ||