The workbench compiles the C core from Clara's renditionverite project to JavaScript with Emscripten. It runs the interpreter in a Web Worker. A synchronous mailbox adapter replaces host threads; submitted assembly does not execute on the server.
Cycle stepping advances the model to the next SClk edge. Instruction stepping continues until an instruction retires. The F, D, X1, X2 and W display uses the core's pipeline records. A retirement is shown separately from a younger instruction still waiting in W. Fill, Triangle, Pixel and memory timing run through the same device model.
The initial board preset selects the core's 4 MiB reference SGRAM model, CL3, 100 MHz and closed-row scheduling. There is no board ROM. These are emulator settings, not measured V2200 timing.
Registers and instruction bytes follow the C model's byte order. Imported binaries are copied to the specified local-memory address. Framebuffer display reads that memory using the chosen pixel format and stride.
The assembler preserves the PDF instruction encodings. Known differences in the C decoder are shown beside the decoded instruction:
pre reads its offset from bits 23:16 in the C core.Datasheet conflicts are recorded separately. Rendition source references list the original driver files used by this wiki.
F7 steps an instruction. F8 steps a cycle. F9 starts Fast Run or pauses. Ctrl+Enter assembles and loads the source. Breakpoints use byte addresses. Register and memory edits require paused execution.
The default example loads when the page opens and stays paused. Step first cycle records the first edge; cycle history appears once there is a recorded edge. Playback settings accept an interval in milliseconds.
The run limit bounds execution. Reset clears device state, retains the loaded memory and restarts at the program's entry address. Assemble & Load clears memory before loading a new program. The trace keeps the latest 256 records.
Each cycle shows captured operands, forwarded values, pending results and committed register writes. Highlights use the C core's access events, including writes that store the same value. Held stages show their stall reason.
Play cycles advances one SClk edge at a time. Fast Run samples the display while executing at full speed. The cycle history inspects recorded pipeline events; it leaves the device at its current state. The register bank is labelled Live registers, and editing is disabled while inspecting an earlier cycle.
Output stays above the pipeline. Pixels refresh after steps and stops. Recent committed register results remain visible after the program halts. Display settings select the local-memory range, pixel format and zoom; PNG export keeps the original pixel dimensions.