RISC Pipeline
| Stage | Operation |
|---|---|
| F — Fetch | Fetch the next instruction from I-Cache. |
| D — Decode | Decode the instruction and read source operands. |
| X1 — eXecute1 | Perform the operation or calculate a load/store address. |
| X2 — eXecute2 | Second execute cycle for two-cycle instructions. Read load data and load/store tags. |
| W — Write | Write the result to the register file. |
The diagram shows five successive instructions moving through the pipeline. It does not show cache misses, FIFO waits, engine stalls or instruction-specific delays.
A load has an interlocked delay of one instruction. pre, li and lui have no result delay. A scalar multiply launches in one cycle and has a result delay of one; vector multiplies launch in two cycles, with delay zero for the even result and one for the odd result.
Special register hazards are not interlocked. Code must leave the documented interval before reading or using those values. Hazard table lists the required intervals.
Sources: Technical Spec, p.8, Technical Spec, p.9, Technical Spec, p.24