The VGA core supports basic text/graphics modes through mode 13 and mode X. The BIOS provides VESA 2.0 modes through native rendering and display hardware.
Mode.VGA_Mode selects VGA versus native operation. In VGA mode, VGA I/O and memory decode are active; native registers and memory access also remain available. VGA registers retain their state in native mode.
In native mode, VESA_Mode enables VGA register access and the 64 KB window at 0xA0000. BankSelect maps this window onto local memory at eight-KB bank boundaries; bit 31 selects BIOS ROM. When VESA_Mode is clear in native mode, VGA memory and I/O do not decode. VGA blank-status reads return native CRTC status in VESA mode.
| Register group | Index port | Data port |
|---|---|---|
| Sequencer | 0x3C4 | 0x3C5 |
| CRTC, monochrome | 0x3B4 | 0x3B5 |
| CRTC, color | 0x3D4 | 0x3D5 |
| Graphics | 0x3CE | 0x3CF |
| Attribute | 0x3C0 | Write 0x3C0, read 0x3C1 |
The ? in source port names is B for monochrome or D for color. Input Status 0 is not implemented. Extended ports 0x3DE and 0x3DF return native PCI memory base[31:24] and I/O base[15:8]. PCI configuration byte +0x50 controls VGA retry compatibility.
VGA_Extend.Compatibility resets to four and must not be changed. Its Bandwidth bit must also remain at the reset value. FastMode may be set for VGA graphics, but must be clear for VGA text.
Native memory address swizzle is zero; VGA mode uses three, according to MemCtl. Mode-switch state handling is described in Context switching. The source's Attribute table wording is retained in the register pages; standard VGA definitions have not been substituted for conflicting statements.
Complete VGA register map · DAC ports
Sources: Technical Spec, p.43, Technical Spec, p.44, Technical Spec, p.57, Technical Spec, p.58, Technical Spec, p.59, Technical Spec, p.60