The native CRTC reads a local-memory display surface. CRTCCtl selects screen format, sync polarity and enable, video enable, frame mode and FIFO size. Supported screen formats are 8-bit 332/intensity, 16-bit 565/4444/1555 and 32-bit 8888.
CRTCHorz stores horizontal active, back porch, sync and front porch widths in units of eight pixels, minus one. CRTCVert stores their vertical equivalents in scan lines, minus one.
Write CRTCHorz first, then CRTCVert. The horizontal timing takes effect when CRTCVert is written; reads before that return the old horizontal value. These timing registers are not affected by reset.
FrameBaseA is the pixel-aligned top-left byte address. FrameBaseB serves the second stereoscopic frame or odd interlaced field. A write to FrameBaseB commits when FrameBaseA is written; before that, reads return the old value. In stereoscopic mode their low three bits must match.
The VideoFIFO can be 64, 128 or 256 bytes. CRTCCtl bit 23 selects 256 bytes and overrides bit 4. CRTCOffset is a byte offset between the last video FIFO request on a line and the first request on the next. The logical display row width must be a multiple of eight bytes:
StrideOffset = DstStride - ScreenWidth + (ScreenWidth % VideoFifoSize)
+ ((FrameBaseA[2:0] || (ScreenWidth % VideoFifoSize))
? 0 : VideoFifoSize)
Widths in this equation are bytes. CRTCStatus exposes remaining character clocks and scan lines plus the active/front-porch/sync/back-porch phase.
CRTCCtl[6] controls DDCClk: zero drives low; one releases the pin to high impedance, and reads return its pin level. Bit 5 enables DDC data output. With output enabled, bit 7 drives DDCData; otherwise it reads the input pin. The register page shows both meanings.
PLL programming · Palette · Cursor · Digital video output
Sources: Technical Spec, p.45, Technical Spec, p.46, Technical Spec, p.47