Context Switching

The native context procedure first stops new RISC work and waits for all drawing engines. Holding the RISC inserts no-ops after Decode until hazards clear and Pixel/Triangle/Fill become idle. RISCHeld then asserts. This also ensures no FIFO-sourced fill remains active before DMA is disabled.

1. Set Debug.HoldRISC.
2. Wait for chip idle, by polling Status or using IdleIntr.
3. Clear Mode.DMA_En.
4. Save RISC state.
5. While DMA is busy or InputFIFO is nonempty, read and save InputFIFO contents.
6. Read DMACmdPtr, DMA_Address and DMA_Length. The context prose calls the last register DMA_Count; the native map names it DMA_Length.
7. Drain and save OutputFIFO.
8. Read the remaining Pixel Engine and other state.

Before switching to VGA, preserve memory that VGA accesses would overwrite and turn off the hardware cursor. Read CRTCCtl immediately before writing Mode to clear the pipeline, as directed by the specification.

The RISC must be held during StateIndex/StateData accesses. StateIndex selects a readback register. Reading StateData returns that state; writing StateData updates Decode IR instead.

Pixel Engine state is also readable at 0xFFE00800 + index × 8 for the documented entries with a RISC offset. Not every spr selector is a state index. Commands such as IPat and Sync do not represent stored readback registers.

The register catalogue includes all 47 documented readback selectors, their formats and aliases. Reads from unused selectors return unspecified values. Count is unsigned for parallel drawing and signed for parameterized drawing.

For Triangle Engine routines, leave shadowing enabled throughout setup and execution, then disable it before returning to compatibility microcode. Initialize every iterated parameter before each primitive to avoid hidden Triangle Engine state.

StateIndex · StateData · Pixel and context state map

Sources: Technical Spec, p.17, Technical Spec, p.40, Technical Spec, p.42, Technical Spec, p.43, Technical Spec, p.56