====== Digital Video Output ======

Digital video output shares XD[7:0] with XBus. It sends byte-serial 16-bit 565 RGB, most significant byte first, using VOutClk, VOutActive, VOutHSync and VOutVSync. PClkPLL also defines YUVEnable and VOutLSBFirst options.

Enable VOut with [[registers:host-registers:native_pclkpll|PClkPLL[19]]]. Section 9 incorrectly places VOutEn in CRTCCtl; the explicit PLL bit table is used here. Set ExtraDiv2 and program the PLL for the doubled output byte clock. See [[video:clocks|Clock PLLs]].

Analog video and sync continue unless their CRTCCtl enable bits are cleared. Digital HSync and VSync use the analog signal polarities. VOutActive is active high. Disable TestMode when using VOut or XBus.

XBus accesses can still occur with VOut enabled. XBusWaitBlank restricts when accesses start, but the source disagrees on front versus back porch and contains ambiguous polarity wording. [[reference:source_issues|XBUS_BLANK]] preserves the three descriptions.

Sources: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=48|Technical Spec, p.48]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=55|Technical Spec, p.55]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=65|Technical Spec, p.65]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=66|Technical Spec, p.66]]