====== Clock PLLs ======

PClkPLL generates the pixel clock. SClkPLL generates both the system logic clock and memory clock, using separate output dividers. The nominal reference input is 14.318 MHz.

<code>
ClockOut = ((ClockIn / N) * M) / P
</code>

The phase compare frequency (ClockIn/N) must be 1..3 MHz; the oscillator must be 125..250 MHz. MClk must be at least SClk for the domain synchronizers. Wait 200 µs after changing M or N before relying on the new clock.

[[registers:host-registers:native_pclkpll|PClkPLL]] is accessible by host and RISC. [[registers:host-registers:native_sclkpll|SClkPLL]] is read/write through PCI and read only to the RISC. Both retain their programmed values across SoftReset. Hard reset selects PClk 25.165 MHz and initializes SClk/MClk from reset straps.

When digital video output is enabled, ExtraDiv2 supplies an additional divide-by-two before PClk. VOutClk uses the preceding divider output, twice the pixel rate. For a 31.5 MHz pixel rate the source example uses a 126 MHz oscillator, P = 2 and ExtraDiv2 enabled.

The PDF lists default PLL settings for each combination of maximum memory and RISC clock straps. Those exact startup values are in [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=49|Technical Spec, p.49]].

[[video:output|Digital output]] · [[system:reset|Reset configuration]]

Sources: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=47|Technical Spec, p.47]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=48|Technical Spec, p.48]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=49|Technical Spec, p.49]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=61|Technical Spec, p.61]]