====== RISC Programming ======

The RISC is a 32-bit interlocked integer processor with fixed-width, 32-bit instructions. An instruction can perform a scalar operation, two vector operations, a memory transfer, a branch, or a drawing operation. Integer operations are signed unless the instruction specifies otherwise. ALU overflow wraps; there are no instruction exceptions or status register.

===== Register file =====

^ Operand index ^ Use ^
| ''%0..%31'' | Hardwired constants. Writes are ignored. |
| ''%32..%63'' | Special hardware registers, additional constants and undefined indices. |
| ''%64..%127'' | Indirect aliases into ''%128..%255'', selected through ''Seg''. |
| ''%128..%251'' | General purpose registers. |
| ''%252 / sp'' | Stack pointer. |
| ''%253 / ira'' | Interrupt link register. |
| ''%254 / ra'' | Program link register. |
| ''%255 / fp'' | Frame pointer. |

The physical general purpose file contains 128 words. Indirect operand indices are aliases, not another 64 words. ''a0..a31'' and ''q0..q15'' are names for ''%128..%175'' used by the drawing engines.

Special registers are never forwarded. Writes to writable special registers have the non-interlocked hazard specified for that register. ''%32..%46'' may be used as a vector source, but not as a vector destination.

===== Instruction formats =====

The most significant byte is the opcode. The remaining bytes depend on the instruction:

^ Format ^ Bits 31:24 ^ Bits 23:16 ^ Bits 15:8 ^ Bits 7:0 ^
| Integer / draw / jmprl | OP | D | S2 | S1 |
| Store | OP | offset8 | S2 | S1 |
| Load | OP | D | offset8 | S1 |
| Sort | OP | S3 | S2 | S1 |
| li / lui | OP | D | immed16 ||
| sprii | OP | immed16 || S1 |
| Branch | OP | offset16 || S1 |
| Relative / absolute jump | OP | address24 |||

For immediate ALU instructions, the S1 byte is an unsigned immediate. Vector operands must be double-word aligned. A ''v'' instruction uses two register pairs; ''vs'' uses the same scalar S1 value for both operations.

[[risc:opcodes|Opcode grid and instruction details]] · [[risc:alu|Integer operations]] · [[risc:memory|Loads and stores]] · [[risc:branches|Branches and jumps]] · [[risc:step|Step instructions]] · [[risc:special_registers|Special registers]]

Sources: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=5|Technical Spec, p.5]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=6|Technical Spec, p.6]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=7|Technical Spec, p.7]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=8|Technical Spec, p.8]]