====== lh / 0x71 ======

[[risc:opcodes|Opcode map]]

^ Property ^ Definition ^
| OP | ''0x71'' |
| Operands | ''D,offset8(S1)'' |
| Operation | Unsigned halfword load; address=S1+offset8*2; halfword aligned |
| Timing | load interlock 1; pre/li/lui 0 |

[[risc:hazards|Instruction hazards]] · [[registers:opcodes:start|Instruction formats]]

Source: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=9|Technical Spec, p.9]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=10|Technical Spec, p.10]]