====== Byte Order ======

The RISC is big endian. Host control-register offsets are defined for little-endian access. Byte swapping is controlled separately for direct memory access, FIFO aliases and DMA data.

^ Selector ^ Swap ^ Use described by the source ^
| 0 | None | Word data |
| 1 | B3↔B0, B2↔B1 | Byte data; preserves byte addresses between x86 and V2200 |
| 2 | B3↔B2, B1↔B0 | Swap bytes within half-words |
| 3 | B3↔B1, B2↔B0 | Half-word data; preserves half-word addresses |

[[registers:host-registers:native_memendian|MemEndian[1:0]]] controls direct PCI-to-local-memory access. It does not change I/O registers. FIFO alias addresses select their own swap. The low two bits of each DMA length word select swapping for that transfer and are ignored for link commands.

Packed foreground/background data and Fill Engine source data place the left pixel in the most significant portion of a word. Palette RGB word writes use red at 23:16, green at 15:8 and blue at 7:0.

[[host:interface|Host apertures]] · [[host:dma|DMA format]] · [[risc:memory|RISC loads/stores]]

Sources: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=5|Technical Spec, p.5]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=39|Technical Spec, p.39]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=40|Technical Spec, p.40]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=41|Technical Spec, p.41]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=50|Technical Spec, p.50]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=52|Technical Spec, p.52]]