====== PCI Bus-Master DMA ======

DMA transfers host data into InputFIFO from a chained list of command pairs. Write the physical byte address of the first list to [[registers:host-registers:native_dmacmdptr|DMACmdPtr]], with Mode.DMA_En enabled. LowWaterMark must be at least three.

A command occupies eight bytes and must be double-word aligned. The even word is DMAAddress; the odd word is DMALength. A list must fit within one aligned 16 KB block.

^ DMALength bits ^ Definition ^
| 31 | One selects a link to another command list; zero selects a data transfer. |
| 30:24 | Ignored. |
| 23:2 | Transfer length in words; ignored for a link. |
| 1:0 | Data byte-swap selector; ignored for a link. |

DMAAddress is a word-aligned physical byte address for transfer data, or a pointer to the next command list. A link with a null address terminates DMA. The source states a maximum transfer length of 16 MB.

DMABusy asserts immediately when DMACmdPtr is written with a non-null pointer. It remains asserted until completion or stopping. Clearing Mode.DMA_En stops DMA. On completion, DMACmdPtr points to the last command. Completion can be tested through DMACmdPtr.DMABusy, MemEndian.DMABusy or DMAIntr.

DMA_Address and DMA_Length expose the current data address and remaining transfer count. These registers are read only. During a context switch, draining InputFIFO may be necessary after disabling DMA; use the [[system:context|specified save sequence]].

[[registers:dma-formats:start|Command-pair bit diagram]] · [[registers:host-registers:native_mode|Mode]] · [[registers:host-registers:native_lowwatermark|LowWaterMark]] · [[host:endian|Swap selectors]]

Source: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=50|Technical Spec, p.50]]