====== Interface Timing ======

These are external signal timings. They are separate from RISC result delays and drawing-engine launch times.

===== Memory Write =====

Measured at the memory chips. All values are minimum nanoseconds.

^ Symbol ^ Signal / condition ^ V2200 ^ V2200-60 ^
| ts | Data setup before write | 4.0 | 3.0 |
| th | Data hold after write | 2.5 | 1.5 |
| tdsz | Data setup from tri-state | 3.5 | 2.5 |
| tcs | Control/address setup | 4.0 | 3.0 |
| tch | Control/address hold | 2.6 | 1.6 |

Source waveform: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=63|Technical Spec, p.63]]

===== Memory Read =====

Measured at V2200. All values are minimum nanoseconds.

^ Symbol ^ Condition ^ V2200 ^ V2200-60 ^
| trds | Data setup | 2.0 | 1.75 |
| trdh | Data hold | 2.0 | 1.75 |

The figure caption on page 64 says memory write, but its table and signals describe memory read.

Source waveform: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=64|Technical Spec, p.64]]

===== Video Input =====

^ Symbol ^ Signals ^ Minimum ^
| tvs | Setup for VIn[7:0], Active, VBlank, HSync and VSync before VInClk | 5.0 ns |
| tvh | Hold for those signals after VInClk | 0.0 ns |

Source waveform: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=65|Technical Spec, p.65]]

===== XBus =====

BClk in these expressions is the PCI clock period in nanoseconds.

^ Symbol ^ Condition ^ Time (ns) ^
| txwp | Minimum write pulse | 4 × BClk − 3 |
| txrp | Minimum read pulse | 4 × BClk − 3 |
| txads | Address setup before access; data setup before write | 2 × BClk − 3 |
| txadh | Address hold after access; data hold after write | 2 × BClk − 3 |
| txrs | Read data setup to XRd or XWait | 10 |
| txrh | Read data hold from XRd | 0 |
| txp | Minimum precharge between accesses | 3 × BClk − 3 |

Source waveform: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=66|Technical Spec, p.66]]

[[hardware:interfaces|PCI timing and interface signals]] · [[hardware:electrical|Electrical characteristics]]