====== Pin Assignments ======

The table includes all 320 pins from the source pin-out. VSS ranges and the VDD list are expanded into individual positions. “n.c.” retains the source marking.

^ Pin ^ Signal ^ Pin ^ Signal ^ Pin ^ Signal ^ Pin ^ Signal ^
| A1 | V5V | A2 | XD[1] | A3 | XD[6] | A4 | XA[0] |
| A5 | XReset# | A6 | VOutVSync | A7 | VOutActive | A8 | MD[1] |
| A9 | MD[5] | A10 | MD[9] | A11 | MD[10] | A12 | MD[13] |
| A13 | MDQM[0]# | A14 | MDQM[3]# | A15 | MD[18] | A16 | MD[22] |
| A17 | MD[25] | A18 | MD[26] | A19 | MD[31] | A20 | RCS# |
| B1 | DirectMClk | B2 | XD[2] | B3 | XD[3] | B4 | XD[7] |
| B5 | XA[1] | B6 | XWr# | B7 | VOutHSync | B8 | MD[0] |
| B9 | MD[4] | B10 | MD[8] | B11 | MD[12] | B12 | MD[14] |
| B13 | MDQM[1]# | B14 | MD[16] | B15 | MD[19] | B16 | MD[23] |
| B17 | MD[29] | B18 | MD[30] | B19 | MDSF | B20 | MCS[1]# |
| C1 | PCLKPLLVDD | C2 | DirectPClk | C3 | XD[0] | C4 | XD[4] |
| C5 | XWait# | C6 | XA[2] | C7 | XRd# | C8 | VOutClk |
| C9 | MD[3] | C10 | MD[7] | C11 | MD[11] | C12 | MD[15] |
| C13 | MDQM[2]# | C14 | MD[17] | C15 | MD[21] | C16 | MD[24] |
| C17 | MD[28] | C18 | MCS[0]# | C19 | MRAS# | C20 | MClkOut[0] |
| D1 | PCLKPLLVSS | D2 | XtalOut | D3 | XtalIn | D4 | VDD |
| D5 | XD[5] | D6 | VDD | D7 | XA[3] | D8 | VDD |
| D9 | MD[2] | D10 | MD[6] | D11 | VDD | D12 | MClkIn[0] |
| D13 | VDD | D14 | MD[20] | D15 | VDD | D16 | MD[27] |
| D17 | VDD | D18 | MCAS# | D19 | MClkOut[1] | D20 | MD[33] |
| E1 | DACComp | E2 | VDDA | E3 | VDDA | E4 | VDD |
| E17 | MWE# | E18 | MD[32] | E19 | MD[34] | E20 | MD[37] |
| F1 | BGRO | F2 | VDDA | F3 | VDDA | F4 | VDDA |
| F17 | VDD | F18 | MD[35] | F19 | MD[38] | F20 | MD[40] |
| G1 | DACVRef | G2 | VDDA | G3 | VDDA | G4 | Blue |
| G7 | VSS | G8 | VSS | G9 | VSS | G10 | VSS |
| G11 | VSS | G12 | VSS | G13 | VSS | G14 | VSS |
| G17 | MD[36] | G18 | MD[39] | G19 | MD[41] | G20 | MD[42] |
| H1 | DACIRef | H2 | MCLKPLLVDD | H3 | VSSA | H4 | VSSA |
| H7 | VSS | H8 | VSS | H9 | VSS | H10 | VSS |
| H11 | VSS | H12 | VSS | H13 | VSS | H14 | VSS |
| H17 | VDD | H18 | MD[43] | H19 | MD[44] | H20 | MD[45] |
| J1 | DDCClk | J2 | VSSA | J3 | VSSA | J4 | Green |
| J7 | VSS | J8 | VSS | J9 | VSS | J10 | VSS |
| J11 | VSS | J12 | VSS | J13 | VSS | J14 | VSS |
| J17 | MD[46] | J18 | MD[47] | J19 | MDQM[4]# | J20 | MClkIn[1] |
| K1 | DDCData | K2 | HSync | K3 | VSSA | K4 | VSSA |
| K7 | VSS | K8 | VSS | K9 | VSS | K10 | VSS |
| K11 | VSS | K12 | VSS | K13 | VSS | K14 | VSS |
| K17 | MDQM[5]# | K18 | MDQM[6]# | K19 | MDQM[7]# | K20 | MD[48] |
| L1 | VSync | L2 | XIntr# | L3 | VSSA | L4 | Red |
| L7 | VSS | L8 | VSS | L9 | VSS | L10 | VSS |
| L11 | VSS | L12 | VSS | L13 | VSS | L14 | VSS |
| L17 | VDD | L18 | MD[50] | L19 | MD[51] | L20 | MD[49] |
| M1 | EvenFrame | M2 | VIn[6] | M3 | VIn[5] | M4 | VSSA |
| M7 | VSS | M8 | VSS | M9 | VSS | M10 | VSS |
| M11 | VSS | M12 | VSS | M13 | VSS | M14 | VSS |
| M17 | MD[55] | M18 | MD[54] | M19 | MD[53] | M20 | MD[52] |
| N1 | VIn[7] | N2 | VIn[3] | N3 | VIn[2] | N4 | VDD |
| N7 | VSS | N8 | VSS | N9 | VSS | N10 | VSS |
| N11 | VSS | N12 | VSS | N13 | VSS | N14 | VSS |
| N17 | VDD | N18 | MD[58] | N19 | MD[57] | N20 | MD[56] |
| P1 | VIn[4] | P2 | VIn[1] | P3 | VInClk | P4 | VDD |
| P7 | VSS | P8 | VSS | P9 | VSS | P10 | VSS |
| P11 | VSS | P12 | VSS | P13 | VSS | P14 | VSS |
| P17 | MA[0] | P18 | MD[61] | P19 | MD[60] | P20 | MD[59] |
| R1 | V5V | R2 | VInHSync | R3 | VInActive | R4 | VDD |
| R17 | VDD | R18 | MA[1] | R19 | MD[63] | R20 | MD[62] |
| T1 | VIn[0] | T2 | n.c. | T3 | VInVBlank | T4 | VDD |
| T17 | MA[7] | T18 | MA[4] | T19 | MA[3] | T20 | MA[2] |
| U1 | VInVSync | U2 | n.c. | U3 | n.c. | U4 | VDD |
| U5 | n.c. | U6 | VDD | U7 | Req# | U8 | VDD |
| U9 | AD[24] | U10 | VDD | U11 | BClk | U12 | IRdy# |
| U13 | VDD | U14 | AD[12] | U15 | VDD | U16 | AD[6] |
| U17 | VDD | U18 | MA[8] | U19 | MA[9] | U20 | MA[5] |
| V1 | n.c. | V2 | n.c. | V3 | n.c. | V4 | n.c. |
| V5 | n.c. | V6 | Gnt# | V7 | AD[29] | V8 | AD[26] |
| V9 | CBE[3]# | V10 | AD[21] | V11 | AD[17] | V12 | Frame# |
| V13 | Stop# | V14 | AD[15] | V15 | AD[11] | V16 | AD[8] |
| V17 | AD[5] | V18 | AD[2] | V19 | MA[10] | V20 | MA[6] |
| W1 | n.c. | W2 | n.c. | W3 | n.c. | W4 | n.c. |
| W5 | IntA# | W6 | AD[31] | W7 | AD[28] | W8 | V5V |
| W9 | IDSEL | W10 | AD[22] | W11 | AD[18] | W12 | CBE[2]# |
| W13 | DevSel# | W14 | CBE[1]# | W15 | AD[14] | W16 | AD[10] |
| W17 | CBE[0]# | W18 | AD[4] | W19 | AD[1] | W20 | MA[11] |
| Y1 | n.c. | Y2 | n.c. | Y3 | n.c. | Y4 | n.c. |
| Y5 | Rst# | Y6 | AD[30] | Y7 | AD[27] | Y8 | AD[25] |
| Y9 | AD[23] | Y10 | AD[20] | Y11 | AD[19] | Y12 | AD[16] |
| Y13 | TRdy# | Y14 | Par | Y15 | V5V | Y16 | AD[13] |
| Y17 | AD[9] | Y18 | AD[7] | Y19 | AD[3] | Y20 | AD[0] |

The package drawing uses a top view, 1.27 mm pitch and 27.00 mm outline. It labels 320 solder-resist openings of diameter 0.635 mm.

Signal naming differs between the pin-out and preceding sections in a few places, including RCS# / ROMCS# and XIntr# / XIntr. The table retains the pin-out names.

[[https://verite.3d32.org/_media/source/v2200spec.pdf#page=68|Technical Spec, p.68]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=69|Technical Spec, p.69]]

[[hardware:interfaces|Interface groups]] · [[hardware:electrical|Supply and reference connections]]