====== Hardware Interfaces ======

^ Interface ^ Signals / width ^ Source ^
| PCI | AD[31:0], C/BE[3:0]#, Frame#, IRdy#, TRdy#, Stop#, parity and arbitration | [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=62|Technical Spec, p.62]] |
| Memory | MD[63:0], MA[11:0], two chip selects, eight byte masks, memory command signals and clocks | [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=63|Technical Spec, p.63]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=64|Technical Spec, p.64]] |
| ROM | RD[7:0], RA[16:0], ROMOE#, ROMWE#, ROMCS#; shares memory data pins | [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=64|Technical Spec, p.64]] |
| Video input | Eight-bit data plus Active, VBlank, HSync, VSync and VInClk | [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=65|Technical Spec, p.65]] |
| Video output | Analog RGB, sync, DDC; byte-serial digital output on XD[7:0] | [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=65|Technical Spec, p.65]] |
| XBus | XD[7:0], XA[3:0], read/write strobes, wait, interrupt and reset | [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=66|Technical Spec, p.66]] |

XBus exposes a sixteen-byte external-device window at native I/O +0xF0..+0xFF. Host byte, half-word and word operations become one, two and four external byte accesses, beginning at the lowest address. TestMode must be disabled when using XBus, VIn or VOut.

The PCI description calls the chip a 66 MHz device and gives a minimum BClk period of 15 ns, but its BClk prose also says “up to 33 MHz.” Both statements appear on page 62. Board clock capability must not be inferred from that prose alone.

===== Signal timing =====

^ Parameter ^ Minimum ^ Maximum ^
| PCI Gnt# setup | 5 ns | — |
| Other PCI setup | 3 ns | — |
| PCI hold | 0 ns | — |
| PCI output delay | 2 ns | 6 ns |
| BClk period | 15 ns | — |
| VIn signal setup / hold | 5 ns / 0 ns | — |

Memory write timings are measured at the memory chips; read timings are measured at V2200. The PDF lists separate values for V2200-60. XBus pulse and precharge times are expressed in BClk periods. Use the original waveform tables for board timing; these values are not RISC instruction cycle counts.

===== Supply and package =====

Digital and analog supplies are 3.135..3.465 V. The V5V latch-up supply is 4.75..5.25 V. XtalIn is not five-volt tolerant. The source recommends a separate 3.3 V analog regulator for DAC/PLL isolation.

The package drawing gives a 27.00 mm outline, 1.27 mm pitch and 320 solder-resist openings. [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=68|Pin assignments]] and [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=69|mechanical drawing]] remain available in the source PDF.

Sources: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=62|Technical Spec, p.62]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=63|Technical Spec, p.63]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=64|Technical Spec, p.64]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=65|Technical Spec, p.65]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=66|Technical Spec, p.66]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=67|Technical Spec, p.67]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=68|Technical Spec, p.68]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=69|Technical Spec, p.69]]

[[hardware:pinout|All pin assignments]] · [[hardware:timing|Memory, video and XBus timing]] · [[hardware:electrical|Electrical tables]]