====== Build a DMA List ======

Transfer 64 words (256 bytes) from host physical address ''0x00108000'' into InputFIFO, with no payload byte swap. Place the command list at host physical address ''0x00100000''.

These addresses are example allocations. They must refer to DMA-accessible host memory; they are not RISC local-memory addresses.

===== Command Words =====

^ Host physical address ^ Word ^ Value ^
| ''0x00100000'' | DMAAddress, even word | ''0x00108000'' |
| ''0x00100004'' | DMALength, odd word | ''0x00000100'' |
| ''0x00100008'' | Link address, even word | ''0x00000000'' |
| ''0x0010000C'' | Link command, odd word | ''0x80000000'' |

The list is eight-byte aligned and fits within the aligned 16 KB block ''0x00100000..0x00103FFF''. The payload address is word aligned.

^ DMALength field ^ Transfer command ^ Terminating link ^
| Bit 31, link flag | 0 | 1 |
| Bits 30:24 | 0, ignored | 0, ignored |
| Bits 23:2, word count | 64 | Ignored |
| Bits 1:0, byte swap | 0, no swap | Ignored |

<code c>
#include <stdint.h>

/* PCI word values at the four addresses above. */
static const uint32_t command_words[4] = {
    0x00108000u,
    (64u << 2) | 0u,       /* 0x00000100: transfer, 64 words, no swap */
    0x00000000u,
    0x80000000u            /* Link to null: terminate */
};
</code>

The transfer count is ''(DMALength >> 2) & 0x003FFFFF''. Multiplying by four gives 256 bytes. The two low bits select swapping of **payload data** and are ignored for links. These command words are PCI DWORD values, separate from a serialized RISC instruction stream.

===== Starting and Completing =====

Set [[registers:host-registers:native_lowwatermark|LowWaterMark]] to at least three and enable [[registers:host-registers:native_mode|Mode.DMA_En]]. Writing ''0x00100000'' to [[registers:host-registers:native_dmacmdptr|DMACmdPtr]] starts this list and asserts DMABusy.

The RISC must consume InputFIFO data for a transfer larger than its FIFO capacity. At completion, DMABusy clears and DMACmdPtr points to the final command. Completion can also raise DMAIntr when enabled. Host physical allocation, PCI bus-master enable and board startup are prerequisites, not supplied by this packet.

Source: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=25|Technical Spec, p.25]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=40|Technical Spec, p.40]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=43|Technical Spec, p.43]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=44|Technical Spec, p.44]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=50|Technical Spec, p.50]]

[[registers:dma-formats:start|Command-pair diagram]] · [[host:dma|DMA reference]] · [[examples:start|Examples]]