====== Decode an Instruction Word ======

[[tools:risc#example-signed-multiply|Open the multiply program in the workbench]].

Decode ''0x18C8C9CA''. Its RISC byte sequence is ''18 C8 C9 CA''.

^ Bits ^ Value ^ Interpretation ^
| 31:24 | ''0x18'' | Scalar ''mul'' opcode |
| 23:16 | ''0xC8'' | D = ''%200'' |
| 15:8 | ''0xC9'' | S2 = ''%201'' |
| 7:0 | ''0xCA'' | S1 = ''%202'' |

<code asm>
; Initial values: %201 = 0xFFFFFFFE (-2), %202 = 3.
mul %200, %201, %202       ; Encoded word: 0x18C8C9CA.
</code>

With S2 = ''0xFFFFFFFE'' and S1 = ''0x00000003'', the signed 64-bit product is ''0xFFFFFFFFFFFFFFFA''. Scalar ''mul'' keeps its low 32 bits, so D becomes ''0xFFFFFFFA'' (−6). Launch takes one cycle and the result has delay one.

Sources: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=5|Technical Spec, p.5]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=8|Technical Spec, p.8]]

===== Byte Order =====

The RISC is big endian: bytes at successive RISC addresses A..A+3 are ''18'', ''C8'', ''C9'', ''CA''. A decoder receiving a word value starts with ''0x18C8C9CA''; a decoder receiving bytes must assemble them in that order.

Host memory and FIFO transfers have separate swap controls. Their selector must match the host data representation; [[host:endian|MemEndian, FIFO aliases and DMA swapping]] describe those controls.

Source: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=5|Technical Spec, p.5]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=39|Technical Spec, p.39]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=41|Technical Spec, p.41]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=50|Technical Spec, p.50]]

===== An Immediate Is Unsigned =====

''0x00C8C9FF'' selects ''add immediate'', D = %200, S2 = %201, immediate = ''0xFF''. It adds **255**, not −1. Starting with S2 = −2 produces D = 253 (''0x000000FD'').

Source: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=8|Technical Spec, p.8]]

===== A Branch Offset Is Signed =====

''0x63FFFEC8'' selects ''blz'', S1 = %200, offset16 = ''0xFFFE'' (−2). At PC ''0x00000100'', the delay-slot PC is ''0x00000104''. The taken target is:

<code>
0x00000104 + (-2 * 4) = 0x000000FC
</code>

The instruction at ''0x104'' executes before control transfers. The branch is taken if %200 is negative. Unlike the ALU immediate, this offset is sign-extended.

Source: [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=6|Technical Spec, p.6]], [[https://verite.3d32.org/_media/source/v2200spec.pdf#page=11|Technical Spec, p.11]]

[[risc:opcode:18|mul]] · [[risc:opcode:00|add immediate]] · [[risc:opcode:63|blz]] · [[examples:start|Examples]]